Abstract
A distinguishing characteristic of field-programmable logic is the ability to route wires in the field, but previous authors have made compelling arguments for routing packets, not wires, between major system components. The present paper outlines the packet-switched network for interconnecting heterogeneous nodes in QuickSilver Technology’s Adaptive Computing Machine (ACM). Special attention is paid to two truly innovative aspects of the ACM architecture: (1) the Point-to-Point (PTP) protocol for transferring real-time, streaming data and (2) the node wrapper which makes all nodes appear homogeneous regardless of their internal structure or functionality. The wrapper also provides a single, uniform and consistent mechanism for task management, flow control and load balancing across all node types. With the PTP protocol and the node wrapper, nodes as diverse as digital signal processors, reduced-instruction-set processors, domain-specific processors, reconfigurable fabrics, on-chip and off-chip bulk memories and input/output ports can communicate seamlessly. Moreover, once a node (including wrapper) has been configured, or reconfigured, by a supervisory node, it is able to operate autonomously without the need for global control.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Seitz, C.L.: Let’s Route Packets Instead of Wires. In: Dally, W.J. (ed.) Proceedings of the 6th MIT Conference on Advanced Research in VLSI, pp. 133–137. MIT Press, Cambridge (1990)
Dally, W., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Proc. Design Automation Conf., pp. 684–689 (June 2001)
Master, P.: The Age of Adaptive Computing is Here. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 1–3. Springer, Heidelberg (2002)
Guccione, S.A.: The Adaptive Computing Machine Combines DSP Programmability with the Power and Performance of Custom Hardware. In: Global Signal Processing Expo and Conference (GSPx), Dallas, TX (2003)
Dennis, J.B.: First Version of a Data Flow Procedure Language. In: Robinet, B. (ed.) Programming Symposium. LNCS, vol. 19, pp. 362–376. Springer, Heidelberg (1974)
Dennis, J.B.: The Evolution of ’Static’ Data-Flow Architecture. In: Gaudiot, J.-L., Bic, L. (eds.) Advanced Topics in Data-Flow Computing, pp. 35–91. Prentice-Hall, Englewood Cliffs (1991)
Leiserson, C.E.: Fat-trees: Universal Networks for Hardware-Efficient Supercomputing. IEEE Transactions on Computers C-34(10), 892–901 (1985)
Petri, C.A.: Kommunikation mit Automaten: Institut für Instrumentelle Mathematik, Schriften des IIM Nr. 2, Bonn (1962)
Lysaght, P., Dunlop, J.: Dynamic Reconfiguration of Field Programmable Gate Arrays. In: Moore, W., Luk, W. (eds.) Proceedings of the 1993 International Workshop on Field- Programmable Logic and Applications, Oxford (1993)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Furtek, F., Hogenauer, E., Scheuermann, J. (2004). Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_15
Download citation
DOI: https://doi.org/10.1007/978-3-540-30117-2_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
eBook Packages: Springer Book Archive