Abstract
In this chapter, we describe effective logic testing algorithms for relatively small (less than ten two-input NAND gate equivalent) hardware Trojan detection. Conventional post-manufacturing testing, test generation algorithms, and test coverage metrics cannot be readily extended to hardware Trojan detection. To reduce this lacuna, a novel test pattern generation technique termed multiple excitation of rare occurrence (MERO) is introduced, which maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Extending this approach and addressing some of the shortcomings of MERO, an enhanced automatic test pattern generation (ATPG) scheme using genetic algorithm and Boolean satisfiability is described and evaluated.
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Govindan, V., Chakraborty, R.S. (2018). Logic Testing for Hardware Trojan Detection. In: Bhunia, S., Tehranipoor, M. (eds) The Hardware Trojan War. Springer, Cham. https://doi.org/10.1007/978-3-319-68511-3_7
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DOI: https://doi.org/10.1007/978-3-319-68511-3_7
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