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Advances in Memristors, Memristive Devices and Systems pp 449–476Cite as

Analysis of Dynamic Linear Memristor Device Models

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Part of the book series: Studies in Computational Intelligence ((SCI,volume 701))

Abstract

The aim of this book chapter is to provide a comprehensive review report on the Memristor device. Development of linear model for memristor and analysis of memristor are the prime focus as its current requirement for high speed and low power circuits design. Detailed discussion about memristor device physics, structure, operation, mathematical modeling and TCAD simulations have been carried out for better understand of memristor. Moore’s law, the semiconductor industry’s obsession with the shrinking of transistors with the commensurate steady doubling on chip about every two years, has been a source of about 50 year technical and economic revolution. Numerous innovations by a large number of scientists and engineers have helped significantly to sustain Moore’s law since the beginning of the Integrated Circuit (IC) era. As the cost of computer power to the consumer reduces, the cost of production for producers to sustain Moore’s law follows an opposite trend, i.e. Research, Development, Manufacturing, and Test costs are increasing continuously with each new generation of chips. This had led to the reason for existence of Moore’s second law, also called Rock’s law, which is that the capital cost of a semiconductor fabrication also increases exponentially over time. The formation of memristor is a great achievement in semiconductor industry considering Moore’s second law because of its very easy and less steps of fabrication which is the reason for memristor being so cheap, while its nano scale size is new direction to attain Moore’s first law. Therefore, the modelling and simulation of memristor is essential to analyze more advanced features of memristor without spending a lot of money on fabrication and testing.

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Author information

Authors and Affiliations

  1. Department of Electronics and Communication, National Institute of Technology, Jalandhar, 144011, Punjab, India

    Balwinder Raj

  2. R & D Centre, Vel Tech University, #42, Avadi, Chennai, 600062, Tamil Nadu, India

    Sundarapandian Vaidyanathan

Authors
  1. Balwinder Raj
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  2. Sundarapandian Vaidyanathan
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Correspondence to Sundarapandian Vaidyanathan .

Editor information

Editors and Affiliations

  1. Research and Development Centre, Vel Tech University Research and Development Centre, Chennai, India

    Sundarapandian Vaidyanathan

  2. Department of Physics, Aristotle University of Thessaloniki Department of Physics, Thessaloniki, Greece

    Christos Volos

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Raj, B., Vaidyanathan, S. (2017). Analysis of Dynamic Linear Memristor Device Models. In: Vaidyanathan, S., Volos, C. (eds) Advances in Memristors, Memristive Devices and Systems. Studies in Computational Intelligence, vol 701. Springer, Cham. https://doi.org/10.1007/978-3-319-51724-7_18

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  • DOI: https://doi.org/10.1007/978-3-319-51724-7_18

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-51723-0

  • Online ISBN: 978-3-319-51724-7

  • eBook Packages: EngineeringEngineering (R0)

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