Abstract
Computer vision has emerged as one of the most popular domains of embedded applications. The applications in this domain are characterized by complex, intensive computations along with very large memory requirements. Parallelization and multiprocessor implementations have become increasingly important for this domain, and various powerful new embedded platforms to support these applications have emerged in recent years. However, the problem of efficient design methodology for optimized implementation of such systems remains vastly unexplored. In this chapter, we look into the main research problems faced in this area and how they vary from other embedded design methodologies in light of key application characteristics in the embedded computer vision domain.We also provide discussion on emerging solutions to these various problems.
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References
Altilar D, Paker Y (2001) Minimum overhead data partitioning algorithms for parallel video processing. In: Proc. of 12th Intl. Conf. on Domain Decomposition Methods, 2001.
Auguin M, Bianco L, Capella L, Gresset E (2000) Partitioning conditional data flow graphs for embedded system design. In: IEEE Intl. Conf. on Application-Specific Systems, Architectures, and Processors, 2000, pp. 339-348.
Auguin M, Capella L, Cuesta F, Gresset E (2001) CODEF: a system level design space exploration tool. In: Proc. of IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing, May 7-11, 2001, vol. 2, pp. 1145-1148.
Baloukas C, Papadopoulos L, Mamagkakis S, Soudris D (2007) Component based library implementation of abstract data types for resource management customization of embedded systems. In: Proc. of IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, Oct. 2007, pp. 99-104.
Berekovic M, Flugel S, Stolberg H.-J, Friebe L, Moch S, Kulaczewski M.B, Pirsch P (2003) HiBRID-SoC: a multi-core architecture for image and video applications. In: Proc. of 2003 Intl. Conf. on Image Processing, Sept. 14-17, 2003.
Bhattacharya B, Bhattacharyya S S (2000) Parameterized dataflow modeling of DSP systems. In Proc. of the Intl. Conf. on Acoustics, Speech, and Signal Processing, Istanbul, Turkey, Jun. 2000, pp. 1948-1951.
Bhattacharya B, Bhattacharyya S S (2000) Quasi-static scheduling of reconfigurable dataflow graphs for DSP systems. In: Proc. of the Intl. Wkshp. on Rapid System Prototyping, Paris, France, Jun. 2000, pp. 84-89.
Bhattacharyya S S, Leupers R, Marwedel P (2000) Software synthesis and code generation for signal processing systems. IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, Sept. 2000, vol. 47, issue 9, pp. 849-875.
Bhattacharyya S S, Murthy P K, Lee E A (1996) Software Synthesis from Dataflow Graphs, Boston, MA, Kluwer.
Bilsen G, tEngels M, Lauwereins R, Peperstraete J (1994) Static scheduling of multi-rate and cyclostatic DSP applications. In:Wkshp. on VLSI Signal Processing, 1994, pp. 137-146.
Bilsen G, Engels M, Lauwereins R, Peperstraete J (1996) Cyclo-static dataflow. IEEE Trans. on Signal Processing, Feb. 1996, vol. 44, no. 2, pp. 397-408.
Clarke E M, Grumberg O, Peled D (1999) Model Checking, MIT Press, Cambridge, MA.
Crisman J.D, Webb J.A (1991) The warp machine on Navlab. IEEE Trans. Pattern Analysis and Machine Intelligence, May 1991, vol. 13, no. 5, pp. 451-465.
Daniels M, Muldawert K, Schlessman J, Ozert B, Wolf W (2007) Real-time human motion detection with distributed smart cameras. In: First ACM/IEEE Intl. Conf. on Distributed Smart Cameras, Sept. 25-28, 2007.
Davie A (1992) An Introduction to Functional Programming Systems Using Haskell, Cambridge University Press, New York, NY.
Duffy D A (1991) Principles of Automated Theorem Proving, John Wiley and Sons, New York, NY.
Dutta S, Connor K.J, Wolf W, Wolfe A (1998) A design study of a 0.25-μm video signal processor. IEEE Trans. on Circuits and Systems for Video Technology, vol. 8, Aug. 1998, issue 4, pp. 501-519.
Dutta S, Wolf W, Wolfe A (1998) A methodology to evaluate memory architecture design tradeoffs forvideo signal processors. IEEE Trans. on Circuits and Systems for Video Technology, Feb. 1998, vol. 8, issue 1, pp. 36-53.
Denolf K, Bekooji M, Cockx J, Verkest D, Corporaal H(2007) Exploiting the expressiveness of cyclo-static dataflow to model multimedia implementations. EURASIP Journal on Advances in Signal Processing, doi:10.1155/2007/84078.
Eker J, Janneck J W (2003) CAL Language Report: Specification of the CAL Actor Language. Technical Memorandum No. UCB/ERL M03/48, University of California, Berkeley, CA, 94720, USA, Dec. 1, 2003.
Franke B, Boyle M. O(2001) An empirical evaluation of high level transformations for embedded processors. In: Proc. of Intl. Conf. on Compilers, Architecture and Synthesis for Embedded Systems, Nov. 2001.
Franke B, Boyle M. O(2003) Array recovery and high-level transformations for DSP applications. ACM TECS, vol. 2, May 2003, pp. 132-162.
Geilen M, Basten T(2004) Reactive process networks. In: Proc. of the Intl. Wkshp on Embedded Software, Sept. 2004, pp. 137-146.
Halbwachs N (1993) Synchronous Programming of Reactive Systems, Kluwer Academic Publishers, Norwell, MA.
Hammerstrom D.W, Lulich D.P (1996) Image processing using one-dimensional processor arrays. Proc. of the IEEE, July 1996, vol. 84, no. 7, pp. 1005-1018.
Han M, Kanade T (2001) Multiple motion scene reconstruction from uncalibrated views. In: Proc. 8th IEEE Intl. Conf. on Computer Vision, vol. 1, 2001, pp. 163-170.
Henriksson T, Wolf P. V. D (2006) TTL hardware interface: a high-level interface for streaming multiprocessor architectures. In: Proc. of IEEE/ACM/IFIP Wkshp. on Embedded Systems for Real Time Multimedia, Oct. 2006, pp. 107-112.
Ho W. H, Lee E. A, Messerschmitt D G (1988) High level data flow programming for digital signal processing. In: Proc. of the Intl. Wkshp. on VLSI Signal Processing, 1988.
Hsu C, Bhattacharyya S S (2005) Porting DSP applications across design tools using the dataflow interchange format. In: Proc. of the Intl. Wkshp. on Rapid System Prototyping, Montreal, Canada, Jun. 2005, pp. 40-46.
Hsu D, Ko M, Bhattacharyya S S (2005), Software Synthesis from the Dataflow Interchange Format. In: Proc. of the Intl. Wkshp. on Software and Compilers for Embedded Systems, Dallas, Texas, Sept. 2005, pp. 37-49.
Hu X, Greenwood G W, Ravichandran S, Quan G (1999) A framwork for user assisted design space exploration. In: Proc. of 36th Design Automation Conf., New Orleans, Jun. 21-25, 1999.
Hu X, Marculescu R (2004) Adaptive data partitioning for ambient multimedia. In: Proc. of Design Automation Conf., June 7-11, 2004, San Diego, California, USA.
Jerraya A A, Wolf W (2005) Hardware/Software interface codesign for embedded systems. Computer, Feb. 2005, vol. 38, issue 2, pp. 63-69.
Kalavade A, Lee E (1995) The extended partitioning problem: hardware/software mapping and implementation-bin selection. In: Proc. of Intl. Wkshp. on Rapid System Prototyping, Jun. 7-9, Chapel Hill, NC, 1995.
Kapasi U J, Rixner S, Dally W J, Khailany B, Ahn J H, Mattson P, Owens J D (2003) Programmable stream processors. Computer, vol. 35, no. 8, Aug. 2003, pp. 54-62.
Karkowski I, Corporaal H (1998) Design space sxploration slgorithm for heterogeneous multi-processor embedded system design. In: Proc. of 35th Design Automation Conf., San Francisco, Jun. 15-18, 1998.
Keinert J, Haubelt C, Teich J (2006) Modeling and analysis of windowed synchronous algorithms. In: Proc. of the Intl. Conf. on Acoustics, Speech, and Signal Processing, May 2006.
Ko D, Bhattacharyya S S (2005) Modeling of block-based DSP systems. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Jul. 2005, vol. 40(3), pp. 289-299.
Ko D, Bhattacharyya S S (2006). The pipeline decomposition tree: An analysis tool for multiprocessor implementation of image processing applications. In: Proc. of the Intl. Conf. on Hardware/Software Codesign and System Synthesis, Seoul, Korea, Oct. 2006, pp. 52-57.
Ko M-Y, Shen C-C, Bhattacharyya S S (2006). Memory-constrained block processing for DSP software optimization. In: Proc. of Embedded Computer Systems: Architectures, Modeling and Simulation, Jul. 2006, pp. 137-143.
Kshirsagar S P, Harvey D M, Hartley D A, Hobson C. A (1994) Design and application of parallel TMS320C40-based image processing system. In: Proc. of IEE Colloquium on Parallel Architectures for Image Processing, 1994.
Kumar A, Mesman B, Corporaal H, Theelen B, Ha Y (2007) A probabilistic approach to model resource contention for performance estimation of multifeatured media devices. In: Proc. of Design Automation Conf., Jun. 4-8, San Diego, USA.
Kung S Y (1988) VLSI Array Processors, Prentice Hall, NJ.
Kuzmanov G K, Gaydadjiev G N, Vassiliadis S (2005) The Molen media processor: design and evaluation. In: Proc. of the Intl. Wkshp. on Application Specific Processors, 2005, New York Metropolitan Area, USA, Sept. 2005, pp. 26-33.
Kwon S, Lee C, Kim S, Yi Y, Ha S (2004) Fast design space exploration framework with an efficient performance estimation technique. In: Proc. of 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004, pp. 27-32.
Lee C, Wang Y, Yang T (1994) Static global scheduling for optimal computer vision and image processing operations on distributed-memory multiprocessors. Tech. Report: TRCS94-23, University of California at Santa Barbara, Santa Barbara, CA, USA.
Lee C, Yang T, Wang Y (1995) Partitioning and scheduling for parallel image processing operations. In: Proc. of the 7th IEEE Symp. on Parallel and Distributeed Processing, 1995.
Lee E A, Messerschmitt D G (1987) Static scheduling of synchronous dataflow programs for digital signal processing. IEEE Transactions on Computers, vol. C-36, no. 2, Feb. 1987.
Lee H G, Ogras U Y, Marculescu R, Chang N (2006) Design space exploration and prototyping for on-chip multimedia applications. In: Proc. of Design Automation Conf., Jul. 24-28, 2006, San Francisco, USA,
Marwedel P (2002) Embedded software: how to make it efficient. In: Proc. of the Euromico Symp. on Digital System Design, Sept. 2002, pp. 201-207.
Milner R, Tofte M, Harper R (1990) The Definition of Standard ML, MIT Press, Cambridge, MA.
Miramond B, Delosme J (2005) Design space exploration for dynamically reconfigurable architectures. In: Proc. of Design Automation and Test in Europe, 2005, pp. 366-371.
Murphy C W, Harvey D M, Nicholson L J (1999) Low cost TMS320C40/XC6200 based reconfigurable parallel image processing architecture. In: Proc.of IEEE Colloquium on Reconfigurable Systems, Mar. 10, 1999.
Murthy P K, Lee E A (2002) Multidimensional synchronous dataflow. IEEE Trans. on Signal Processing, Aug. 2002, vol. 50, no. 8, pp. 2064-2079.
Neuendorffer S (2002) Automatic Specialization of Actor-Oriented Models in Ptolemy II. Master’s Thesis, Dec. 2002, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley.
Niemann R, Marwedel P(1997) An algorithm for hardware/hoftware partitioning using mixed integer linear programming. Design Automation for Embedded Systems, vol. 2, no. 2, Kluwer, Mar. 1997.
Ng K, Ishigurob H, Trivedic M, Sogo T (2004) An integrated surveillance system – human tracking and view synthesis using multiple omni-directional vision sensors. Image and Vision Computing Journal, Jul. 2004, vol. 22, no. 7, pp. 551-561.
Oh H, Ha S (2004), Fractional rate dataflow model for efficient code synthesis. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, May 2004, vol. 37, pp. 41-51.
Oh H, Ha S (2002) Efficient code synthesis from extended dataflow graphs for multimedia applications. In: Proc. of 39th Design Automation Conference, 2002, pp. 275-280.
Panda P R, Catthoor F, Dutt N D, Danckaert K, Brockmeyer E, Kulkarni C, Vandercappelle A, Kjeldsberg P G (2001) Data and memory optimization techniques for embedded systems. ACM Trans. on Design Automation of Electronic Systems, Apr. 2001, vol. 6, no. 2, pp. 149-206.
Parhi K K (1995) High-level algorithm and architecture transformations for DSP synthesis. Journal of VLSI Signal Processing, vol. 9(1), pp. 121-143, Jan. 1995.
Parks T M, Pino J L, Lee E A (1995) A comparison of synchronous and cyclo-static dataflow. In Proc. of IEEE Asilomar Conf. on Signals, Systems, and Computers, Pacific Grove, CA, Oct. 29-Nov. 1, 1995.
Peixoto H. P, Jacome M. F(1997) Algorithm and architecture-level design space exploration using hierarchical data flows. In: Proc. of IEEE Intl. Conference on Application-Specific Systems, Architectures and Processors, Jul. 14-16, 1997, pp. 272-282.
Pham D C, Aipperspach T, Boerstler D, Bolliger M, Chaudhry R, Cox D, Harvey P, Harvey P M, Hofstee H P, Johns C, Kahle J, Kameyama A, Keaty J, Masubuchi Y, Pham M, Pille J, Posluszny S, Riley M, Stasiak D L, Suzuoki M, Takahashi O, Warnock J, Weitzel S, Wendel D, Yazawa K, (2006) Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. Journal of solid-state circuits, Jan. 2006, vol. 41, issue 1, pp. 179-196.
Pino J L, Bhattacharyya S S, Lee E A (1995) A hierarchical multiprocessor scheduling system for DSP applications. In: Proc. of the IEEE Asilomar Conf. on Signals, Systems, and Computers, Nov. 1995, vol.1, pp. 122-126.
Raman B, Chakraborty S, Ooi W T, Dutta S (2007) Reducing data-memory footprint of multimedia applications by delay redistribution. In: Proc. of 44th ACM/IEEE Design Automation Conference, Jun. 4-8, 2007, San Diego, CA, USA, pp. 738-743.
Rim M, Jain R (1996) Valid transformations: a new class of loop transformations for high-level synthesis and pipelined scheduling applications. IEEE Trans. on Parallel and Distributed Systems, Apr. 1996, vol. 7, pp. 399-410.
Ritz S, Pankert M, Zivojnovic V, Meyr H (1993) Optimum vectorization of scalable synchronous dataflow graphs. In: Proc. of Intl. Conf. on Application-Specific Army Processors, 1993, pp. 285-296.
Saha S (2007) Design Methodology for Embedded Computer Vision Systems. PhD Thesis, University of Maryland, College Park, Dec. 2007.
Saha S, Kianzad V, Schessman J, Aggarwal G, Bhattacharyya S S, Wolf W, Chellappa R. An architectural level design methodology for smart camera applications. Intl. Journal of Embedded Systems, Special Issue on Optimizations for DSP and Embedded Systems, (To appear).
Saha S, Puthenpurayil S, Bhattacharyya S S (2006) Dataflow transformations in high-level DSP system design. In: Proc. of the Intl. Symp. on System-on-Chip, Tampere, Finland, Nov. 2006, pp. 131-136.
Saha S, Puthenpurayil S, Schlessman J, Bhattacharyya S S, Wolf W (2007) An optimized message passing framework for parallel implementation of signal processing applications. In: Proc. of the Design, Automation and Test in Europe, Munich, Germany, Mar. 2008.
Schlessman J, Chen C-Y, Wolf W, Ozer B, Fujino K, Itoh K (2006) Hardware/Software co-Design of an FPGA-based embedded tracking system. In: Proc. of 2006 Conf. on Computer Vision and Pattern Recognition Wkshp., Jun. 17-22, 2006.
Sriram S, Bhattacharyya S S (2000) Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker Inc, New York, NY.
Teoh E K, Mital D P (1993) Real-time image processing using transputers. In: Proc. of Intl. Conf. on Systems, Man and Cybernetics, Oct. 17-20, 1993, pp. 505-510.
Torre A. D, Ruggiero M, Benini L, Acquaviva A (2007) MP-Queue: an efficient communication library for embedded streaming multimedia platforms. In: Proc. of IEEE/ACM/IFIP Wkshp. on Embedded Systems for Real-Time Multimedia, Oct. 4-5, 2007, pp. 105-110.
Velmurugan R, Subramanian S, Cevher V, Abramson D, Odame K. M, Gray J D, Lo H-J, McClellan J H, Anderson D V (2006) On low-power analog implementation of particle filters for target tracking. In: Proc. 14th European Signal Processing Conf., Sep. 2006.
Velmurugan R, Subramanian S, Cevher V, McClellan J H, Anderson D V (2007) Mixed-mode implementation of particle filters. In: Proc. of IEEE PACRIM Conf., Aug. 2007.
Wadge W, Ashcroft E. A (1985) Lucid, The Dataflow Programming Language, Academic Press, San Diego, CA.
Wardhani A W, Pham B L, (2002) Progamming optimisation for embedded vision. In:Proc. of DICTA2002: Digital Image Computing Techniques and Applications, Melbourne, Australia, Jan. 21-22, 2002.
Wiggers M H, Bekooji M J G, Smit G J M (2007) Efficient computation of buffer capacities for cyclo-static dataflow graphs. In: Proc. of Design Automation Conf., Jun. 4-8, San Diego, USA.
Xian C, Lu Y, Li Z (2007) Energy-aware scheduling for real-time multiprocessor systems with uncertain task execution time. In: Proc. of Design Automation Conf., Jun. 4-8, San Diego, USA.
Youssef M, Sungjoo Y, Sasongko A, Paviot Y, Jerraya A A (2004) Debugging HW/SW interface for MPSoC: video encoder system design case study. In: Proc. of 41st Design Automation Conf., 2004, pp. 908- 913.
Zamora N H, Hu X, Marculescu R (2007) System-level performance/power analysis for platform-based design of multimedia applications. ACM Trans. on Design Automation of Electronic Systems, Jan. 2007, vol. 12, no. 1, article 2.
Ziegenbein D, Ernest R, Richter K, Teich J, Thiele L(1998) Combining multiple models of computation for scheduling and allocation. In: Proc. of Codes/CASHE 1998, pp. 9-13.
Wong W (2007) Architecture Maps DSP Flow To Parallel Processing Platform. In: Electronic Design, May 10, 2007.
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Saha, S., Bhattacharyya, S.S. (2009). Design Methodology for Embedded Computer Vision Systems. In: Kisačanin, B., Bhattacharyya, S.S., Chai, S. (eds) Embedded Computer Vision. Advances in Computer Vision and Pattern Recognition. Springer, London. https://doi.org/10.1007/978-1-84800-304-0_2
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