VHDL Background for Synthesis

Abstract

This chapter will review the basic VHDL concepts used for simulation and synthesis of ASICs, in preparation for succeeding chapters which show their usage in various applications. The material presented is intended for designers with little or no previous VHDL experience, and covers both the language and various logic design and synthesis concepts as they relate to VHDL usage. Experienced VHDL users can skip over some of the VHDL syntax portions but should read the sections on synthesis of clocked and combinational logic, latches and registers, since they deal with general logic synthesis guidelines.