Abstract
In this chapter, we will evaluate the digital phase-locked loops for phase inputs similar to the analysis of analog phase-locked loops in Chapter 4. This analysis will be on linearized transfer functions, and applies to the complete digital loops of Chapter 9 as well as the analog/digital phase-locked loops of Chapter 8.
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References
Lindsey, W.C., Chie, C.M., “A Survey of Digital Phase-Locked Loops”, Proceedings of the IEEE, Vol. 69, No. 4, pp. 410–430, April 1981.
Chie, C.M., Analysis of Digital Phase-Locked Loops, Ph.D. Dissertation, University of Southern California, January, 1977.
Weinberg, A., Liu, B., “Discrete Time Analyses of Nonuniform Sampling First-and Second-Order Digital Phase Lock Loops”, IEEE Transactions on Communications, Vol. COM-22, No. 2, pp. 123–137, February, 1974.
McCain, B.W., McGillem, C.D., “Performance Improvements of DPLL’s in Non-Gaussian Noise Using Robust Estimators”, IEEE Transactions on Communications, Vol. COM-35, No. 11, pp. 1207–1216, November 1987.
Papoulis, A., Probability, Random Variables, And Stochastic Processes, Second Edition, New York, NY, McGraw-Hill Book Company, 1984.
Jeruchim, M.C., Balaban, P., Shanmugan, K.S., Simulation of Communication Systems, New York, NY, Plenum Press, 1992.
Whichman, B., Hill, D. “Building a Random-Number Generator”, BYTE Magazine, pp. 127–128, March, 1987.
Coates, R.F.W., Janacek, G.J,. Lever, K.V., “Monte Carlo Simulation and Random Number Generation”, IEEE Journal on Selected Areas in Communications, Vol. 6, No. 1, pp. 58–66, January, 1988.
Box, G.E.P., Muller, M.E., “A Note On the Generation of Random Normal Deviates”, Annals of Mathematical Statistics, Vol. 29, No. 2, pp. 610–611, June, 1958.
Charles, F.J., Lindsey, W.C., “Some Analytical and Experimental Phase-Locked Loop Results for Low Signal-Noise Ratios”, Proceedings of the IEEE, vol. 54, no. 9, pp. 1152–1166, September, 1966.
Welti, A.L., Bernhard, U.P., Bobrovsky, B., “Third-Order Delay-Locked Loop: Mean Time to Lose Lock and Optimal Parameters”, IEEE Transactions on Communications, Vol. 43, No. 9, pp. 2540–2550, September 1995.
Sarkar, B.C., Chattopadhyay, S., “A New Look Into the Acquisition Properties of a Second-Order Digital Phase Locked Loop”, IEEE Transactions on Communications, Vol. 42, No. 5, pp. 2087–2091, September 1995.
Osborne, H.C., “Stability Analysis of an Nth Power Digital Phase-Locked Loop-Part II: Second and Third-Order DPLLs”, IEEE Transactions on Communications, Vol. COM-28, pp. 1355–1364, August 1980.
Sarkar, B.C., Chattopadhyay, S., “Acquisition Problem of Class of Second-Order Digital Phase-Locked Loops”, Electronics Letters, Vol. 25, pp. 552–553, April 1989.
Chie, M.C., “Mathematical Analogies Between First-Order Digital and Analog Phase-Locked Loops”, IEEE Transactions on Communications, Vol. COM-26, No. 6, pp. 860–865, June 1978.
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Stephens, D.R. (1998). Digital PLL Responses and Acquisition. In: Phase-Locked Loops for Wireless Communications. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5717-3_10
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DOI: https://doi.org/10.1007/978-1-4615-5717-3_10
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