Skip to main content
SpringerLink
Log in
Book cover

Low Power Design Methodologies pp 37–64Cite as

Low Power Circuit Techniques

  • Chapter

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 336))

Abstract

When CMOS (Complementary Metal Oxide Semiconductor) technology was originally introduced, low power was one of the main motivations [32]. CMOS circuits was the first (and only) digital circuit technique which did not consume any static power. Power was only consumed when the circuit was switched. By using CMOS it was believed that the power consumption problem was solved. Since then, integrated circuit complexity and speed have been continuously increased. One result of this is that also CMOS now approaches the limits of acceptable power consumption [10]. We will therefore investigate the power consumption of CMOS circuits in this chapter, and make some brief comparisons with other circuit techniques.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M. Afghahi, J. Yuan, Double edge-triggered D-flip-flops for High Speed CMOS Circuits, IEEE J. of Solid-State Circuits, Vol. 26, No. 8 pp 1168–1170, 1991.

    Article  Google Scholar 

  2. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Reading, Addison-Wesley Publishing Company, 1990.

    Google Scholar 

  3. T Blalock and J Jaeger, A High-Speed Clamped Bitline Current-Mode Sense Amplifier, IEEE J. of Solid State Circuits, Vol. 26, pp 542–548, 1991.

    Article  Google Scholar 

  4. A. Chandrakasan, S. Sheng and R. W. Brodersen, Low-Power CMOS Digital Design, IEEE Journal of Solid-State Circuits Vol. 27, No. 4, 1992.

    Google Scholar 

  5. A. Chandrakasan et al Design of Portable Systems, Proc. of IEEE 1994 Custom Integrated Circuits Conference, pp 12.1.1–12.1.8, 1994.

    Google Scholar 

  6. J.-S. Choi and K. Lee, Design of CMOS tapered Buffer for Minimum Power-Delay Product, IEEE Journal of Solid-State Circuits Vol. 29, No. 9, pp 1142–1145, 1988.

    Article  Google Scholar 

  7. K. M. Chu and D. L. Pulfrey, A Comparison of CMOS Circuits Techniques: Differential Cascade Voltage Switch Logic Versus Conventional Logic, IEEE J. of Solid-State Circuits, Vol. 22, No. 4, pp 528–532, 1992.

    Article  Google Scholar 

  8. E. De Man and M. Schöbinger, Power Dissipation in the Clock System of Highly Pipe-lined CMOS Circuits, Proc. 1994 Int. workshop on Low Power Design, pp133–138.

    Google Scholar 

  9. D. Deschacht, M. Robert, and D. Auvergne, Explicit Formulation of Delay in CMOS Data Paths, IEEE Journal of Solid-State Circuits Vol. 23, No. 5, pp 1257–1264, 1988.

    Article  Google Scholar 

  10. D. W. Dobberpuhl et al, A 200-MHz 64-b Dual-Issue CMOS Microprocessor, IEEE J. of Solid-State Circuits, Vol. 27, No. 11, pp 1555–1566, 1992.

    Article  Google Scholar 

  11. Draft 1.00 IEEE Std 1596.3–1994, IEEE Standard for Low-Voltage Differential Signal for SCI (LVDS).

    Google Scholar 

  12. M. A. Ortega and J. Figueras, Bounds on the Harzard Power Consumption in Modular Static CMOS Circuits, a talk on PATMOS’94, Barcelona, Spain, unpublished.

    Google Scholar 

  13. N. F. Goncalves, H. J. DeMan, NORA: A Race-free Dynamic CMOS Technique for Pipelined Logic Structures, IEEE J. of Solid-State Circuits, Vol. 18, June 1983.

    Google Scholar 

  14. N. Hedenstierna and K. Jeppson, CMOS Circuit Speed and Buffer Optimization, IEEE Tr. of Computer Aided Design, Vol. 6, March 1987, pp. 270–281.

    Article  Google Scholar 

  15. R. Hossain, L. D. Wronski, and A. Albicki, Low Power Design Using Double Edge Triggered Flip-Flops, IEEE Tr. on VLSI Systems, Vol.2, No. 2, 1994, pp 261–265.

    Article  Google Scholar 

  16. M. Ishibe et al. High-Speed CMOS I/O Buffer Circuits, IEEE J. of Solid-State Circuits, Vol. 27, No. 4, pp 671–673, 1992.

    Article  Google Scholar 

  17. P. Larsson, C. Svensson, Noise in Digital Dynamic CMOS Circuits, IEEE Journal of Solid-State Circuits, Vol. 29. No. 6, pp 655–662, 1994.

    Article  Google Scholar 

  18. W. Lee et al, A Comparative Study on CMOS Digital Circuit Families for Low Power Applications, Proc. 1994 Int. workshop on Low Power Design, pp129–132.

    Google Scholar 

  19. D. Liu, C. Svensson, Comparison of power consumption in CMOS synchronous logic circuits, Proc. of European workshop on power and timing modelling pp 31–37, 1992

    Google Scholar 

  20. D. Liu, C. Svensson, Trading Speed for Low Power by Choice of Supply and Threshold Voltages, IEEE Journal of Solid-State Circuits Vol. 28, No. 1, pp 10–17, 1993.

    Article  Google Scholar 

  21. D. Liu, C. Svensson, Power Consumption Estimation in CMOS VLSI Chips, IEEE Journal of Solid-State Circuits Vol. 29, No. 6, pp 663–670, 1994.

    Article  Google Scholar 

  22. C. Metra, Minimal Power-Delay Product CMOS Buffer, 4th International Workshop on PATMOS, Oct. 1994, Barcelona, pp 150–157.

    Google Scholar 

  23. Y. Nakagome et al. Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI’s, IEEE Journal of Solid-State Circuits Vol. 28, No. 4, pp 414–419, 1993.

    Article  Google Scholar 

  24. C. Piguet, J-M. Masgonty, S. Cserveny, E. Dijkstra, Low-Power Low-Voltage Digital CMOS Cell Design, 4th Int. Workshop on PATMOS, Oct. 1994, Barcelona, pp 132–139.

    Google Scholar 

  25. D. Renshaw and C. H. Lau, Race-Free Clocking of CMOS Pipelines Using a Single Global Clock, IEEE J of Solid-State Circuits, Vol. 25, No. 3, pp 766–769, 1990.

    Article  Google Scholar 

  26. W. Roethig, E. Melcher, and M. Dana, Probabilistic Power Consumption Estimations in Digital Circuits, Proc. European Workshop on power and timing modelling pp 7–15, 1992.

    Google Scholar 

  27. M. S. J. Steyaert et al., ECL-CMOS and CMOS-ECL Interface for 150-MHz Digital ECL Data Transmission Systems, IEEE JSSC, Vol. 26, No. 1, pp 18–23, 1991.

    Google Scholar 

  28. C Svensson and J Yuan, High Speed CMOS Chip to Chip Communication Circuit, Proc. 1991 Int. Symp. on Circuits and Systems, pp. 2221–2231.

    Google Scholar 

  29. N. Tan and S. Eriksson, Low Power Chip-to-Chip Communication Circuits, Electronics Letters, Vol. 30, No. 21, 1994, pp 1732–1733.

    Article  Google Scholar 

  30. P. Vanoostende et al, Evaluation of the limitations of the simple CMOS power estimation formula: comparison with accurate estimation, Proc. European workshop on power and timing modelling pp 16–25, 1992.

    Google Scholar 

  31. H. J. M. Veendrick, Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of buffer circuits, IEEE JSSC Vol. 19, No.4, 1984.

    Google Scholar 

  32. N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design, (Second edition), Reading, Addison-Wesley Publishing Company, 1993.

    Google Scholar 

  33. M Winzker, Influence of Statistical Properties of Video Signals on the Power Dissipation of CMOS Circuits, Proc. of PATMOS’94, Barcelona, 17–19 Oct. 1994, pp 106–113.

    Google Scholar 

  34. K. Yano, et al, A 3.8-ns CMOS 16X16-b Multiplier Using Complementary Pass-Transistor Logic, IEEE J. of Solid-State Circuits, Vol. 25, No. 2, pp 388–395, 1990.

    Article  Google Scholar 

  35. J. Yuan C. Svensson, High Speed CMOS Circuit Techniques, IEEE J. of Solid-State Circuits, Vol. 24, No. 1, 1989, pp 62–70.

    Article  Google Scholar 

  36. J. Yuan, C. Svensson and P. Larsson, New domino logic precharged by clock and data, Electronics Letters, Vol. 29, No. 25, pp 2188–2189, 1993.

    Article  Google Scholar 

Download references

Authors
  1. Christer Svensson
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Dake Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. University California, USA

    Jan M. Rabaey

  2. University of Southern California, USA

    Massoud Pedram

Rights and permissions

Reprints and permissions

Copyright information

© 1996 Springer Science+Business Media New York

About this chapter

Cite this chapter

Svensson, C., Liu, D. (1996). Low Power Circuit Techniques. In: Rabaey, J.M., Pedram, M. (eds) Low Power Design Methodologies. The Springer International Series in Engineering and Computer Science, vol 336. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2307-9_3

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-2307-9_3

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5975-3

  • Online ISBN: 978-1-4615-2307-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation