Abstract
Thanks to the short-channel effect suppression of nanowire FET (NWFET), it has become a candidate for the next-generation VLSI device. Different types of NWFETs are introduced to meet the system requirements, with pros and cons. The bottom-up-processed transistor provides the full performance in transistor level, but the integration capability is bounded by the single type of devices per layer and logic design for NMOS and PMOS combined structure is severely restricted. Besides, gate length is relatively large sized, and to overcome this, crossed nanowire transistor-based nanoscale integrated circuit (NASIC) is proposed. Even though this design achieves the minimum area and promises for the large-scale integration so far, the transistor performance is far from the nanotransistor, because of its non-closed gate structure. Top-down process allows flexible design, but the performance and integration are in its early stage. CMOS interface is required to activate the NW logic and to provide signals from/to conventional system.
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Abbreviations
- NWFET:
-
Nanowire FET
- NASIC:
-
Nanotransistor application-specific integrated circuits
- SCE:
-
Short-channel effect
- FPGA:
-
Field-programmable gate array
- GAA:
-
Gate-all-around
- SBD:
-
Schottky barrier diodes
- xNW:
-
Crossing nanowire
- LB:
-
Langmuir–Blodgett
- SNAP:
-
Superlattice nanowire pattern transfer
- MW:
-
Microwire
- PLA:
-
Programmable logic array
- PCM:
-
Phase change memory
- TMR:
-
Triple modular redundancy
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Chung, J. (2014). Nanowire FET Circuit Design: An Overview. In: Kim, D., Jeong, YH. (eds) Nanowire Field Effect Transistors: Principles and Applications. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8124-9_11
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DOI: https://doi.org/10.1007/978-1-4614-8124-9_11
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