Abstract
Design complexity of embedded systems, in particular multiprocessor system-on-chip (MPSoC), has dramatically increased over the years due to feature richness and conflicting design requirements in terms of power, performance and reliability[1]. With such design complexity, traditional design methodology with separate hardware and software design flow is becoming less feasible with high productivity and quality needs. A promising solution to tackle such design complexity is to use a set of modular design techniques during the system specification and preliminary design phases, otherwise known as electronic system-level (ESL) design methodology. ESL design methodology enables concurrent and co-operative design environment of hardware and software components of an MPSoC. Moreover, it provides with overall design space exploration to facilitate reduction of architectural and software partitioning/mapping options early in the design phase, leading to significant improvement in productivity. As a result, currently there is a lot of interest in such design methodology both in academia and industry. In this chapter, an overview of different MPSoC design challenges is given, highlighting ways to address and implement them using ESL design methodology. An extensive systemlevel case study is also presented later highlighting the design trade-offs in low power and reliable MPSoC application design.
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Shafik, R.A., Al-Hashimi, B.M., Chakrabarty, K. (2014). System-Level Design Methodology. In: Mathew, J., Shafik, R., Pradhan, D. (eds) Energy-Efficient Fault-Tolerant Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4193-9_5
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