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Developing Embedded Systems from Formal Specifications Written in Temporal Logic

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 150))

Abstract

We propose a semi-automatic method for developing embedded systems using program code extraction from formal specifications written in temporal logic. This method consists of the following four steps. (1) Write a formal specification for a system. (2) Refine the specification to adapt to the structure and function of the hardware. (3) Obtain a transition system representing a program from the refined specification. (4) Assign program codes to atomic propositions used in the specification, and convert the transition system to the program. As a case study to demonstrate that the proposed method is practical, we generate a program which controls a robot as a line tracer.

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References

  1. McMillan KL (1993) Symbolic model checking. Kluwer Academic Publishers, Norwell

    Book  MATH  Google Scholar 

  2. Tomita T, Hagihara S, Yonezaki N (2011) A probabilistic temporal logic with frequency operators and its model checking. In: Proceedings of the 13th international workshop on verification of infinite-state systems. EPTCS, vol 73. pp 79–93

    Google Scholar 

  3. Abadi M, Lamport L, Wolper P (1989) Realizable and unrealizable specifications of reactive systems. In: Proceedings of 16th international colloquium on automata, languages, and programming. LNCS, vol 372. Springer. pp 1–17

    Google Scholar 

  4. Pnueli A, Rosner R (1989) On the synthesis of a reactive module. In: Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on principles of programming languages. pp. 179–190

    Google Scholar 

  5. Pololu 3pi robot user’s guide, http://www.pololu.com/docs/pdf/0J21/3pi.pdf

  6. Vanitha V, Yamashita K, Fukuzawa K, Yonezaki N (2000) A method for structuralisation of evolutional specifications of reactive systems. In: ICSE 2000. The third international workshop on intelligent software engineering. pp 30–38

    Google Scholar 

  7. Hagihara S, Yonezaki N (2006) Completeness of verification methods for approaching to realizable reactive specifications. In: Proceedings of 1st Asian working conference on verified software AWCVS’06. UNU-IIST, vol 348. pp 242—257

    Google Scholar 

  8. Hagihara S, Kitamura Y, Shimakawa M, Yonezaki N (2009) Extracting environmental constraints to make reactive system specifications realizable. In: Proceedings of the 2009 16th Asia-pacific software engineering conference. APSEC ‘09, IEEE Computer Society. pp 61—68

    Google Scholar 

  9. Lily: a LInear Logic sYnthesizer, http://www.iaik.tugraz.at/content/research/design_verification/lily/

  10. Jobstmann B, Bloem R (2006) Optimizations for LTL synthesis. In: Formal methods in computer aided design, 2006 (FMCAD ‘06). pp 117–124

    Google Scholar 

  11. Koymans R (1990) Specifying real-time properties with metric temporal logic. Real-Time Syst 2(4):255–299

    Article  Google Scholar 

  12. Alur R, Feder T, Henzinger TA (1996) The benefits of relaxing punctuality. J ACM 43(1):116–146

    Article  MathSciNet  MATH  Google Scholar 

  13. Raskin JF, Schobbens PY (1998) The logic of event clocks: decidability, complexity and expressiveness. Automatica 34(3):247–282

    MathSciNet  Google Scholar 

  14. Doyen L, Geeraerts G, Raskin JF, Reichert J (2009) Realizability of real-time logics. In: Proceedings of the 7th international conference on formal modeling and analysis of timed systems. FORMATS ‘09, Springer-Verlag. pp 133–148

    Google Scholar 

  15. Maler O, Nickovic D, Pnueli A (2007) On synthesizing controllers from bounded-response properties. In: Proceedings of the 19th international conference on Computer aided verification (CAV’07). Springer-Verlag, pp 95–107

    Google Scholar 

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Acknowledgments

This work was supported by a Grant-in-Aid for Scientific Research(C) (24500032).

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Correspondence to Shigeki Hagihara .

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Hagihara, S., Arai, T., Shimakawa, M., Yonezaki, N. (2013). Developing Embedded Systems from Formal Specifications Written in Temporal Logic. In: Das, V. (eds) Proceedings of the Third International Conference on Trends in Information, Telecommunication and Computing. Lecture Notes in Electrical Engineering, vol 150. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3363-7_13

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  • DOI: https://doi.org/10.1007/978-1-4614-3363-7_13

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-3362-0

  • Online ISBN: 978-1-4614-3363-7

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