Abstract
SRAM statistical simulation techniques are critical for performance and yield optimization. However, using these techniques to estimate failure probability for SRAM brings many challenges to memory designers. In this chapter, we look at the different statistical techniques used to estimate failure probability, including both conventional and state-of-the-art approaches. As an application of SRAM statistical simulation techniques, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption.
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Notes
- 1.
Here, we assume that there is only random variable that affects circuit operation, however, the concept can be easily extended to multiple dimensions.
- 2.
Details about SRAM dynamic power are presented in Chap. 4.
- 3.
This section focuses on read access yield. Therefore, we use the word yield to refer to read access yield.
- 4.
For detailed analysis on transistor intrinsic noise, the reader is referred to [49].
- 5.
A bold symbol is used to indicate a random variable.
- 6.
Here, we assume that a bank contains one control block that generates WL and SAEN signals as shown in Fig. 5.19. Nevertheless, different types of banking styles can be easily included in the flow.
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Abu-Rahma, M.H., Anis, M. (2013). A Methodology for Statistical Estimation of Read Access Yield in SRAMs. In: Nanometer Variation-Tolerant SRAM. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1749-1_5
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