Introduction

Abstract

Managing power consumption in complex System-on-Chips (SoCs) and custom processors is emerging as the biggest concern for designers. These SoCs and processors are vital parts of embedded systems used in electronic equipments ranging from laptop computers, mobile phones, to personal digital assistants, etc. Quality/Performance of such devices is not only measured by what kind of functionalities these devices are capable of performing, but also how long these gadgets survive without plugging into power outlets for recharging. There is an increased demand for reduced form factor or lower size of such devices, which is generally determined by the size of the battery used to run these devices. Another need for controlling power consumption of the design is to decrease power density of devices on a single die. A survey report [1] shows that power density of some designs can reach the power density of a rocket nozzle in future, if power aware design approaches are not used. The reasons cited above have motivated engineers to look into power aware design methodologies.