Abstract
The scaling of CMOS technology has been the driving force of the semiconductor industry during past five decades, with the minimum feature size expected to reach 10 nm in 10 years [1]. Beyond that benchmark, the present scaling approach may have to take a different route, in order to overcome dramatic barriers in transistor performance degradation, power consumption, process and environmental variations, and reliability issues.
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Cao, Y. (2011). Introduction. In: Predictive Technology Model for Robust Nanoelectronic Design. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0445-3_1
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DOI: https://doi.org/10.1007/978-1-4614-0445-3_1
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