Abstract
The ever-increasing demand for high speed ASICs is driving the requirement to increase circuit throughput in terms of calculations per clock cycle. The performance of an ASIC can be increased by pipelining but at an expense of increase in system latency and area.
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Copyright Maxim Integrated Products ( http://maxim-ic.com ). Used by Permission
References
Application Note AP-589, Design for EMI, Intel®, Feb 1999
Freescale semiconductor application note AN2764, Improving the transient immunity performance of microcontroller-based applications, www.freescale.com, 2005
Application Note 1023, Understanding pipelined ADCs, Maxim, 1 Mar 2001
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© 2012 Springer Science+Business Media, LLC
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Arora, M. (2012). The Art of Pipelining. In: The Art of Hardware Architecture. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0397-5_6
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DOI: https://doi.org/10.1007/978-1-4614-0397-5_6
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