Chapter

Reconfigurable Computing

pp 261-289

Date:

REFLECT: Rendering FPGAs to Multi-core Embedded Computing

  • João M. P. CardosoAffiliated withDepartamento de Engenharia Informática, Faculdade de Engenharia (FEUP), Universidade do Porto Email author 
  • , Pedro C. DinizAffiliated withElectronic Systems Design and Automation Research Group, INESC-ID
  • , Zlatko PetrovAffiliated withAdvanced Technology Europe, Honeywell International
  • , Koen BertelsAffiliated withComputer Engineering Lab, Faculty Electrical Engineering, Mathematics and Computer Science, Technische Universiteit Delft, TUD
  • , Michael HübnerAffiliated withInstitut für Technik der Informationsverarbeitung, Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT)
  • , Hans van SomerenAffiliated withACE Associated Compiler Experts b.v.
  • , Fernando GonçalvesAffiliated withCoreworks – Projectos de Circuitos e Sistemas Electrónicos S.A., CW
  • , José Gabriel F. de CoutinhoAffiliated withDepartment of Computing, Imperial College London
  • , George A. ConstantinidesAffiliated withDepartment of Electrical & Electronic Engineering, Imperial College London
    • , Bryan OlivierAffiliated withACE Associated Compiler Experts b.v.
    • , Wayne LukAffiliated withDepartment of Computing, Imperial College London
    • , Juergen BeckerAffiliated withInstitut fur Technik der Informationsverarbeitung, Fakultat fur Elektrotechnik und Informationstechnik, Karlsruhe Institute für Technology
    • , Georgi KuzmanovAffiliated withComputer Engineering Lab, Faculty Electrical Engineering, Mathematics and Computer Science, Technische Universiteit Delft, TUD
    • , Florian ThomaAffiliated withInstitut für Technik der Informationsverarbeitung, Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT)
    • , Lars BraunAffiliated withInstitut für Technik der Informationsverarbeitung, Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT)
    • , Matthias KühnleAffiliated withInstitut für Technik der Informationsverarbeitung, Fakultät für Elektrotechnik und Informationstechnik, Karlsruher Institut für Technologie (KIT)
    • , Razvan NaneAffiliated withComputer Engineering Lab, Faculty Electrical Engineering, Mathematics and Computer Science, Technische Universiteit Delft, TUD
    • , Vlad Mihai SimaAffiliated withComputer Engineering Lab, Faculty Electrical Engineering, Mathematics and Computer Science, Technische Universiteit Delft, TUD
    • , Kamil KrátkýAffiliated withAdvanced Technology Europe, Honeywell International
    • , José Carlos AlvesAffiliated withDepartamento de Engenharia Electrótecnica, Faculdade de Engenharia (FEUP), Universidade do Porto
    • , João Canas FerreiraAffiliated withDepartamento de Engenharia Electrótecnica, Faculdade de Engenharia (FEUP), Universidade do Porto

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Abstract

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved very often at unreasonably high design efforts. This project covers developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented Specifications to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development as well as program and application portability. We leverage Aspect-Oriented specifications and a set of transformations to generate an intermediate representation suitable to hardware mapping. A programming language, LARA, will allow the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio processing and real-time avionics. We expect the technology developed in REFLECT to be integrated by our industrial partners, in particular by ACE, a leading compilation tool supplier for embedded systems, and by Honeywell, a worldwide solution supplier of embedded high-performance systems.