Abstract
Compiler technologies are crucial for the efficient execution of sequential programs, a statement which is also true for parallel programs. For parallel programs its the operating system performs most of the work. As a result, the overhead for scheduling and distributed shared memory simulation increases. In this chapter we present simple compilation techniques that can be used to guarantee efficient execution of shared memory parallel programs and in particular for multicore machines. We address the difficulties involved with supporting preemption/context-switch of threads in compiled code. Note that preemption is crucial for fair execution of shared memory programs but not necessarily every thread should be preempted repeatedly.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Addison, C., LaGrone, J., Huang, L., Chapman, B.: Openmp 3.0 tasking implementation in Openuh. In: Open64 Workshop at CGO 2009 (2009)
Ayguade, E., Blainey, B., Duran, A., Labarta, J., Martìnez, F., Martorell, X., Silvera, R.: Is the schedule clause really necessary in Openmp? In: Proceedings of the International Workshop on OpenMP Applications and Tools 2003. Lecture Notes in Computer Science, vol. 2716, pp. 69–83 (2003)
Ben-Asher, A.S.Y., Sibeyn, J.F.: Load balancing: A programmer’s approach or the impact of task-length parameters on the load balancing performance of parallel programs. Int. J. High Speed Comput. 7(2), 303–325 (1995)
Berry, G.: Preemption in concurrent systems. In: Foundations of Software Technology and Theoretical Computer Science, pp. 72–93. Springer, Berlin (1993)
Brucker, P.: Scheduling Algorithms. Springer, Berlin (2007). ISBN 354069515X
Burdorf, C., Marti, J.: Non-preemptive Time Warp scheduling algorithms. Oper. Syst. Rev. 24(2), 7–18 (1990)
Culler, D., Karp, R., Patterson, D., Sahay, A., Schauser, K.E., Santos, E., Subramonian, R., von Eiken, T.: LogP: Towards a realistic model of parallel computation. In: Symp. Principles & Practice of Parallel Programming, pp. 1–12 (1993)
Goldstein, S.C., Schauser, K.E., Culler, D.E.: Lazy threads, stacklets, and synchronizers: Enabling primitives for compiling parallel languages. In: Third Workshop on Languages, Compilers, and Run-Time Systems for Scalable Computers (1995)
Goldstein, S.C., Schauser, K.E., Culler, D.E., Lazy threads: Implementing a fast parallel call. J. Parallel Distrib. Comput. 37, 5–20 (1996)
Hauck, E.A., Dent, B.A.: Burroughs’ B6500/B7500 stack mechanism. In: AFIPS Spring Joint Comput. Conf., vol. 32, pp. 245–251 (1968)
Hummel, S.F., Schonberg, E.: Low-overhead scheduling of nested parallelism. IBM J. Res. Dev. 35(5/6), 743–765 (1991)
Hummel, S.F., Schonberg, E., Flynn, L.E.: Factoring: A method for scheduling parallel loops. Commun. ACM 35(8), 90–101 (1992)
Kearns, J.P., Meier, C.J., Soffa, M.L.: The performance evaluation of control implementations. IEEE Trans. Softw. Eng. 8(2), 89–96 (1982)
Krueger, P., Livny, M.: A comparison of preemptive and non-preemptive load distributing. In: Intl. Conf. Distributed Comput. Syst., pp. 123–130 (1988)
Li, T., Baumberger, D., Koufaty, D.A., Hahn, S.: Efficient operating system scheduling for performance-asymmetric multi-core architectures. In: Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, pp. 1–11. ACM, New York (2007)
Mogul, J.C., Borg, A.: The effect of context switches on cache performance. In: Intl. Conf. Architect. Support for Prog. Lang. & Operating Syst., pp. 75–84 (1991)
Muchnick, S.S.: Advanced Compiler Design and Implementation. Morgan Kaufmann, San Mateo (1997). ISBN 1558603204
Pittman, T.: The Art of Compiler Design. Prentice Hall, New York (1992)
Polychronopoulos, C.D.: Parallel Programming and Compilers. Kluwer Academic, Dordrecht (1988)
Reddy, V.K., Sule, A., Anantaraman, A.: Hyper-threading on the Pentium 4. ECE 792E Advanced Microarchitecture (2002)
Tullsen, D.M., Eggers, S.J., Levy, H.M.: Simultaneous multithreading: Maximizing on-chip parallelism. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 392–403. ACM, New York (1995). ISBN 0897916980
Ungerer, T., Robič, B., Šilc, J.: A survey of processors with explicit multithreading. ACM Comput. Surv. 35(1), 29–63 (2003)
Weber, W.-D., Gupta, A.: Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: Preliminary results. In: Ann. Intl. Symp. Computer Architecture Conf. Proc., pp. 273–280 (1989)
Wilhelm, R.: Compiler Design. Addison-Wesley, Reading (1995)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2012 Springer-Verlag London
About this chapter
Cite this chapter
Ben-Asher, Y. (2012). Compilation Techniques. In: Multicore Programming Using the ParC Language. Undergraduate Topics in Computer Science. Springer, London. https://doi.org/10.1007/978-1-4471-2164-0_6
Download citation
DOI: https://doi.org/10.1007/978-1-4471-2164-0_6
Publisher Name: Springer, London
Print ISBN: 978-1-4471-2163-3
Online ISBN: 978-1-4471-2164-0
eBook Packages: Computer ScienceComputer Science (R0)