Abstract
Spin-transfer torque random access memory (STT-RAM) has emerged as a promising technology to replace SRAM and DRAM in embedded memory applications. In STT-RAM, the data are stored in a magnetic device (magnetic tunneling junction or MTJ) as different resistance states. The unique data storage mechanism of STT-RAM introduces the different design optimization concerns from conventional memories. As one important characteristic, programming “1” and “0” into an STT-RAM cell is very asymmetric in terms of performance, power, and reliability. In this chapter, we will review this asymmetry and analyze its sources. The impacts of this asymmetry on the STT-RAM cell optimization will be also discussed, followed by the introduction on a model to simulate the STT-RAM cell asymmetry.
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Acknowledgments
This work was supported by National Science Foundation grants CNS-1116171 and CCF-1217947, and 49th Design Automation Conference A. Richard Newton Scholarship.
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Zhang, Y., Wen, W., Chen, Y. (2014). Asymmetry in STT-RAM Cell Operations. In: Xie, Y. (eds) Emerging Memory Technologies. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9551-3_5
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DOI: https://doi.org/10.1007/978-1-4419-9551-3_5
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