Abstract
Despite the momentum 3D IC technology has gained recently, there has been little progress on timing optimization for 3D ICs. In this chapter, we first study the fact that Through-Silicon-Vias (TSVs) have large parasitic capacitances that increase signal slew. Next, we develop a buffer insertion algorithm that improves the delay of both 3D and 2D nets in a 3D IC with explicit consideration of signal slew. The effectiveness of this technique is demonstrated with various nets and full-chip results. Compared with the well-known van Ginneken algorithm and the timing-constraint-based 2D optimization by a commercial software, our algorithm finds buffering solutions with lower slew-aware delay and buffer usage with tolerable runtime overhead.
The materials presented in this chapter are based on [8].
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Lim, S.K. (2013). Buffer Insertion for 3D IC. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_3
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DOI: https://doi.org/10.1007/978-1-4419-9542-1_3
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