Introduction

Abstract

Over the last decade, real-time digital signal processing has emerged as a key technology with applications in professional and consumer electronics and in telecommunication. The enabling factor for this emergence has been the steady advance in silicon processing technology, and the accompanying increase in computational power of VLSI integrated circuits. Where the initial application field consisted of applications with a low to medium sample rate, such as speech and audio processing, it now also includes applications which run at the rate of video signals. At the same time, and for the same reason, it will soon become possible to integrate a complete system on one chip. In order to keep the design manageable, computer-aided design (CAD) technology needs to be developed. CAD based design methodologies enforce a certain level of formalisation, provide a better documented design, and alleviate the designer from routine and well understood tasks; thus allowing him to concentrate on more creative aspects of the design process. In this book, the problem of synthesising a set of accelerator data paths that are based on a specific architectural style will be investigated. The main optimisation criterion is the minimisation of the silicon area needed to implement the data path, subject to the throughput constraint that is derived from the sample rate of the application. The use of accelerator data paths is critical for high throughput application kernels where the sample rate is close to the achievable clock frequency, and where the number of cycles that are available to map the application is limited to just a few.