Skip to main content

Design for Test by Means of Scan

  • Chapter
  • First Online:
  • 2474 Accesses

Abstract

Most test generation schemes look at a CUT as a black box, the only available nodes of which for testers to control are its primary inputs, and to observe one are its primary outputs. This limited controllability and observability of circuits under test (CUT) means complex test generation algorithms for combinational circuits, and near-impossible test generation for the sequential circuits.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   69.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   89.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   119.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Abramovici M, Breuer MA, Friedman AD (1994) Digital systems testing and testable design. IEEE Press, Piscataway, NJ, revised printing.

    Book  Google Scholar 

  2. Wilkins BR (1986) Testing digital circuits, an introduction. Van Nostrand Reinhold, Berkshire, UK.

    Google Scholar 

  3. Eichelberger EB, Lindbloom E, Waicukauski JA, Williams TW (1991) Structured logic testing. Prentice-Hall, Englewood Cliffs, NJ.

    Google Scholar 

  4. Agrawal VD, Mercer MR (1982) Testability measures – What do they tell us? In: Proceedings of the International Test Conference, Nov 1982, pp 391–396.

    Google Scholar 

  5. Willaims MJY, Angell JB (1973) Enhancing testability of large-scale integrated circuits via test points and additional logic. IEEE Trans Comput C-22(1):46–60.

    Article  Google Scholar 

  6. Miczo A (2003) Digital logic testing and simulation, 2nd edn. Wiley, Hoboken, NJ.

    Book  Google Scholar 

  7. Cheng K-T, Lin C-J (1995) Timing-driven test point insertion for full-scan and partial-scan bist. In: Proceedings of the International Test Conference, Oct 1995, pp 506–514.

    Google Scholar 

  8. Cheng K-T, Agrawal VD ( 1990) A partial scan method for sequential circuits with feedback. IEEE Trans Comput 39(4):544–548.

    Article  Google Scholar 

  9. Narayanan S, Gupta R, Breuer MA (1993) Optimal configuring of multiple scan chains. IEEE Trans Comput 42(9):1121–1131.

    Article  Google Scholar 

  10. Jha NK, Gupta S (2003) Testing of digital systems, Cambridge University Press, Cambridge, UK.

    Book  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Zainalabedin Navabi .

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Navabi, Z. (2011). Design for Test by Means of Scan. In: Digital System Test and Testable Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7548-5_7

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-7548-5_7

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-7547-8

  • Online ISBN: 978-1-4419-7548-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics