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Low-Power Variation-Tolerant Design in Nanometer Silicon pp 41–80Cite as

Power Dissipation

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Abstract

This chapter discusses the power consumption issue of the mainstream CMOS technologies. During the past two decades, power dissipation has stood out as the foremost design challenge for general-purpose and application-specific integrated circuits (ICs). Considering and optimizing the circuit power efficiency has become essential. IC power modeling, analysis, design-time optimization, and run-time management techniques have been intensively studied. This chapter covers the basics of the IC power consumption issue. It first investigates the sources of IC power dissipation, and then discusses recent techniques for IC power analysis. Finally, it studies recently proposed power optimization techniques from circuit and physical design to system synthesis.

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Authors and Affiliations

  1. School of Computer Engineering, Nanyang Technological University, Singapore, Singapore

    Wei Zhang

  2. Department of Electrical, Computer, and Energy Engineering, University of Colorado, Boulder, Co, USA

    James Williamson

  3. Department of Electrical, Computer, and Energy Engineering, University of Colorado, Boulder, Co, USA

    Li Shang

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  1. Wei Zhang
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  2. James Williamson
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  3. Li Shang
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Correspondence to Li Shang .

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Editors and Affiliations

  1. Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Euclid Avenue 10900, Cleveland, 44106-7071, Ohio, USA

    Swarup Bhunia

  2. School of Electrical &, Computer Engineering, Georgia Institute of Technology, Ferst Drive 266, Atlanta, 30332-0250, Georgia, USA

    Saibal Mukhopadhyay

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Zhang, W., Williamson, J., Shang, L. (2011). Power Dissipation. In: Bhunia, S., Mukhopadhyay, S. (eds) Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7418-1_2

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