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Low-Power Techniques for FPGAs

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Book cover Low-Power Variation-Tolerant Design in Nanometer Silicon

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Abstract

Field-programmable gate arrays (FPGAs) are reconfigurable devices that can be programmed after fabrication to implement any digital logic. As such, they are flexible, easy to modify in-field, and cheaper to use than manufacturing a customized application-specific integrated circuit (ASIC). However, this programmability comes at a cost in terms of area, performance, and perhaps most importantly power. As currently manufactured, FPGAs are significantly less power efficient than ASICs. Fortunately, in the last decade concentrated attention to power consumption has identified many approaches to power reduction. This chapter surveys the techniques and progress made to improve FPGA power efficiency.

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Author information

Authors and Affiliations

  1. Department of Computer Science, California Institute of Technology, Pasadena, CA, USA

    Nikil Mehta

  2. Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA, USA

    André DeHon

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  1. Nikil Mehta
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  2. André DeHon
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Correspondence to Nikil Mehta .

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Editors and Affiliations

  1. Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Euclid Avenue 10900, Cleveland, 44106-7071, Ohio, USA

    Swarup Bhunia

  2. School of Electrical &, Computer Engineering, Georgia Institute of Technology, Ferst Drive 266, Atlanta, 30332-0250, Georgia, USA

    Saibal Mukhopadhyay

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Mehta, N., DeHon, A. (2011). Low-Power Techniques for FPGAs. In: Bhunia, S., Mukhopadhyay, S. (eds) Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7418-1_10

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  • DOI: https://doi.org/10.1007/978-1-4419-7418-1_10

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  • Online ISBN: 978-1-4419-7418-1

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