Abstract
Poe’s saying that a long poem is a sequence of short ones is perfectly just.— John Drinkwater
In http://dx.doi.org/10.1007/978-1-4419-6600-1-, we covered basic sequence operators, such as delays, consecutive repetition and disjunction. In this chapter, we learn about the remaining sequence operators. Although these remaining operators do not add any additional expressive power to the language, they are very convenient to use, and make assertions more readable and concise. We also consider sequence methods – constructs that generalize the sampled value function $past for Boolean values to sequences, and discuss using sequences as events.
In examples throughout this chapter, we assume that a default clocking is defined, and thus omit the clock in assertions unless there it is need to emphasize a specific clock usage. We assume that e is a Boolean, r and s are sequences, and p is a property.
Notes
- 1.
It can be proven formally [19].
- 2.
In PSL [6], there is a property operator called next_event with a similar behavior.
- 3.
See Sect. 5.4.1 for a discussion about nested implications.
- 4.
Except when a or b has a match item, see http://dx.doi.org/10.1007/978-1-4419-6600-1-.
- 5.
- 6.
For some tools, it may be more efficient to implement seq _not _first using modeling code to set a flag after clock tick 0.
References
IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language (2005) IEEE Std 1800-2005, pp 1–648
IEC Standard for Property Specification Language (PSL) (Adoption of IEEE Std 1850-2005) (2007) IEC 62531:2007 (E), pp 1–156
IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language (2009) IEEE STD 1800-2009, pp C1–1285
Bustan D, Havlicek J (2006) Some complexity results for systemverilog assertions. In: CAV. pp 205–218
Emerson EA (1990) Temporal and modal logic. In: van Leeuwen J (ed) Handbook of theoretical computer science. Elsevier, pp 996–1072
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2010). Advanced Sequences. In: The Power of Assertions in SystemVerilog. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6600-1_9
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