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Formal Modeling of Embedded Systems with Explicit Schedules and Routes

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Book cover Synthesis of Embedded Software

Abstract

A main goal of compilation is to efficiently map application programs onto execution platforms, while hiding the details of the latter to the programmer through high-level programming languages. Of course this is only feasible inside a certain range of constructs, and the judicious design of sequential programming languages and computer architectures that match one another has been a decades-long process. Now the advent of multicore processors brings radical changes to this topic, bringing forth concurrency as a key element in efficiency, both for application design and architecture computing power. The shift is mostly prompted by technological factors, namely the ability to cram several processors on a single chip, and the diminishing gains of Instruction Level Parallelism techniques used in former architectures. Still, the definition of high-level programming (and more generally, application design) formalisms matching the new era is a largely unsolved issue.

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Notes

  1. 1.

    We recall that \(\mathbb{N} = \left \{0, 1, 2,\ldots \,\right \}\) and \({\mathbb{N}}^{{_\ast}} = \mathbb{N}\setminus \left \{0\right \}\).

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Authors and Affiliations

  1. INRIA Sophia Antipolis Méditerranée, 06902, Sophia Antipolis, France

    Julien Boucaron, Anthony Coadou & Robert de Simone

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  1. Julien Boucaron
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  2. Anthony Coadou
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  3. Robert de Simone
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Correspondence to Robert de Simone .

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  1. Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Whittemore Hall 302, Blacksburg, 24061, USA

    Sandeep K. Shukla

  2. INRIA Rennes-Bretagne Atlantique, Rennes CX, 35042, France

    Jean-Pierre Talpin

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Boucaron, J., Coadou, A., de Simone, R. (2010). Formal Modeling of Embedded Systems with Explicit Schedules and Routes. In: Shukla, S., Talpin, JP. (eds) Synthesis of Embedded Software. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6400-7_2

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