Date: 27 Sep 2012

Designing Chip-Level Nanophotonic Interconnection Networks

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Technology scaling will soon enable high-performance processors with hundreds of cores integrated onto a single die, but the success of such systems could be limited by the corresponding chip-level interconnection networks. There have been many recent proposals for nanophotonic interconnection networks that attempt to provide improved performance and energy-efficiency compared to electrical networks. This chapter discusses the approach we have used when designing such networks, and provides a foundation for designing new networks. We begin by reviewing the basic nanophotonic devices before briefly discussing our own silicon-photonic technology that enables monolithic integration in a standard CMOS process. We then outline design issues and categorize previous proposals in the literature at the architectural level, the microarchitectural level, and the physical level. In designing our own networks, we use an iterative process that moves between these three levels of design to meet application requirements given our technology constraints. We use our ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor-to-DRAM network, and DRAM memory channel to illustrate this design process.