Skip to main content

System On Chip

  • Chapter
  • First Online:
  • 1596 Accesses

Abstract

There is no generally accepted, universally-available machine abstraction above that of a RISC processor. However, the RISC is a key component in a very successful heterogeneous architecture: the System-on-Chip. A system-on-chip architecture combines one or more microprocessors, an on-chip bus system, several dedicated coprocessors, and on-chip memory, all on a single chip. An SoC architecture provides general-purpose computing capabilities along with a few highly specialized functions, adapted to a particular design domain. This chapter reviews the cast of players in the system-on-chip concept, and it describes its key characteristics. The chapter also documents how GEZEL SoC models can be constructed as a combination of custom FSMD hardware modules and simulation primitives to capture the RISC cores.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   59.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  • Claasen T (1999) High speed: not the only way to exploit the intrinsic computational power of silicon. In: Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International, pp 22–25

    Google Scholar 

  • Claasen T (2006) An industry perspective on current and future state of the art in system-on-chip (soc) technology. Proceedings of the IEEE 94(6):1121–1137

    Article  Google Scholar 

  • McKee S (2004) Reflections on the memory wall. In: Conf. Computing Frontiers, pp 162–168

    Google Scholar 

  • Rowen C (2004) Engineering the Complex SOC:Fast, Flexible Design with Configurable Processors. Prentice Hall

    Google Scholar 

  • Saleh R, Wilton S, Mirabbasi S, Hu A, Greenstreet M, Lemieux G, Pande P, Grecu C, Ivanov A (2006) System-on-chip: Reuse and integration. Proceedings of the IEEE 94(6):1050–1069

    Article  Google Scholar 

  • Talla D, Hung CY, Talluri R, Brill F, Smith D, Brier D, Xiong B, Huynh D (2004) Anatomy of a portable digital mediaprocessor. Micro, IEEE 24(2):32–39

    Article  Google Scholar 

  • Vahid F (2009) Dalton project. Tech. rep., http://www.cs.ucr.edu/dalton/

  • Wulf W, McKee S (1995) Hitting the memory wall: Implications of the obvious. In: ACM SIGARCH Computer Architecture News, 23, http://www.cs.virginia.edu/papers/Hitting\_Memory\_Wall-wulf94.pdf

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Patrick R. Schaumont .

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Schaumont, P.R. (2010). System On Chip. In: A Practical Introduction to Hardware/Software Codesign. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6000-9_7

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-6000-9_7

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5999-7

  • Online ISBN: 978-1-4419-6000-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics