Abstract
Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices, such as EEPROM transistors, typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floating-gate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through SiO2, these devices have not seen wide use as memory elements in silicon learning systems.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
T. Allen, A. Greenblatt, C. Mead, and J. Anderson. Writeable analog reference voltage storage device. U.S. Patent No. 5,166,562, 1991.
A. G. Andreou and K. A. Boahen. Analog VLSI signal and information processing. In M. Ismail and T. Fiez, editors, Neural information processing II, pages 358–413. McGraw-Hill, New York, 1994.
S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Masuoka. Reliability issues of flash memory cells. In Proc. of the IEEE, volume 82-5, pages 776–787, 1993.
P. Churchland and T. Sejnowski. The Computational Brain. MIT Press, 1993.
C. Diorio, P. Hasler, B. A. Minch, and C. Mead. A high-resolution non-volatile analog memory cell. In Proc. IEEE Intl. Symp. on Circuits and Systems, volume 3, pages 2233–2236, 1995.
C. Diorio, P. Hasler, B. A. Minch, and C. Mead. A single transistor silicon MOS device for long term learning. U.S. Patent Office serial no. 08/399966, Mar. 7 1995.
C. Diorio, P. Hasler, B. A. Minch, and C. Mead. A single-transistor silicon synapse. IEEE Trans. Electron Devices, 43(11):1972–1980, 1996.
C. C. Enz, F. Krummenacher, and E. A. Vittoz. An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integrated Circuits and Signal Processing, 8:83–114, 1995.
A. S. Grove. Physics and Technology of Semiconductor Devices. John Wiley & Sons, New York, 1967.
P. Hasler, C. Diorio, B. A. Minch, and C. Mead. Single transistor learning synapses. In Advances in Neural Information Processing Systems 7, pages 817–824. MIT Press, Cambridge, MA, 1995.
P. Hasler, C. Diorio, B. A. Minch, and C. Mead. Single transistor learning synapses with long term storage. In IEEE Intl. Symp. on Circuits and Systems, volume 3, pages 1660–1663, 1995.
P. Hasler, B. A. Minch, C. Diorio, and C. Mead. An autozeroing amplifier using pfet hot-electron injection. In Proc. IEEE Intl. Symp. on Circuits and Systems, volume 3, pages 325–328, Atlanta, May 1996.
B. Hochet, V. Peiris, S. Abdo, and M. J. Declercq. Implementation of a learning kohonen neuron based on a new multilevel storage technique. IEEE J. Solid-State Circuits, 26(3):262–267, 1991.
P. Hollis and J. Paulos. A neural network learning algorithm tailored for VLSI implementation. IEEE Tran. Neural Networks, 5(5):784–791, 1994.
J. Lazzaro, J. Wawrzynek, and A. Kramer. Systems technologies for silicon auditory models. IEEE Micro, 14(3):7–15, June 1994.
M. Lenzlinger and E. H. Snow. Fowler-nordheim tunneling into thermally grown sio 2. J. of Appl. Phys., 40(6):278–283, 1996.
F. Masuoka, R. Shirota, and K. Sakui. Reviews and prospects of non-volatile semiconductor memories. IEICE Trans., E 74(4):868–874, 1991.
C. Mead. Scaling of MOS technology to submicrometer feature sizes. J. of VLSI Signal Processing, 8:9–25, 1994.
C. A. Mead. Analog VLSI and Neural Systems. Addison-Wesley, Reading, MA, 1989.
J. J. Sanchez and T. A. DeMassa. Review of carrier injection in the silicon/silicon-dioxide system. In IEE Proceedings-G, volume 138-3, pages 377–389, 1991.
W. Shockley. Problems related to pn junctions in silicon. Solid-State Electronics, 2(1):35–67, 1961.
S. M. Sze. Physics of Semiconductor Devices. John Wiley & Sons, New York, 1981.
E. Takeda, C. Yang, and A. Miura-Hamada. Hot-Carrier Effects in MOS Devices. Academic Press, San Diego, CA, 1995.
S. Tam, P. Ko, and C. Hu. Lucky-electron model of channel hot-electron injection in MOSFET’s. IEEE Trans. Electron Devices, ED-31(9):1116–1125, 1984.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1998 Kluwer Academic Publishers
About this chapter
Cite this chapter
Diorio, C., Hasler, P., Minch, B.A., Mead, C. (1998). Floating-Gate MOS Synapse Transistors. In: Lande, T.S. (eds) Neuromorphic Systems Engineering. The Springer International Series in Engineering and Computer Science, vol 447. Springer, Boston, MA. https://doi.org/10.1007/978-0-585-28001-1_14
Download citation
DOI: https://doi.org/10.1007/978-0-585-28001-1_14
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-8158-7
Online ISBN: 978-0-585-28001-1
eBook Packages: Springer Book Archive