Abstract
Three-dimensional (3D) integration in a system-in-a-package (SiP) implementation (packaging-based 3D) is becoming increasingly used in consumer, computer, and communication applications where form factor is critical. In particular, the hand-held market for a growing myriad of voice, data, messaging, and imaging products is enabled by packaging-based 3D integration (i.e., stacking and connecting individual chips). The key drivers are for increased memory capacity and for heterogeneous integration of different IC technologies and functions.
Keywords
- Wafer Bonding
- Epitaxial Lateral Overgrowth
- Signal Processing Electronic
- Heterogeneous Integration
- Vertical Interconnectivity
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Gutmann, R.J., Lu, JQ. (2009). Wafer-Level 3D Integration for ULSI Interconnects. In: Shacham-Diamand, Y., Osaka , T., Datta, M., Ohba, T. (eds) Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications. Springer, New York, NY. https://doi.org/10.1007/978-0-387-95868-2_6
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