Electrochemical Processing Tools for Advanced Copper Interconnects: An Introduction

Abstract

The change from vacuum-deposited aluminum to electroplated copper in 1997 brought about a paradigm shift in interconnect technology and in chip making [1]. Since then, most of the leading chip manufacturers have converted to electroplated Cu technology for chip interconnects. Cu interconnects are fabricated by dual Damascene process which is referred to a metallization patterning process by which two insulator (dielectric) levels are patterned, filled with copper, and planarized to create a metal layer consisting of vias and lines. The process steps consist of laying a sandwich of two levels of insulator and etch stop layers that are patterned as holes for vias and troughs for lines. They are then filled with a single metallization step. Finally, the excess material is removed, and the wafer is planarized by chemical mechanical polishing (CMP). While finer details of exact sequence of fabrication steps vary, the end result of forming a metal layer remains the same in which vias are formed in the lower layer, and trenches are formed in the upper layer. Electroplating enables deposition of Cu in via holes and overlying trenches in a single step thus eliminating a via/line interface and significantly reducing the cycle time. Due to these reasons and due to relatively less expensive tooling, electroplating is a cost-effective and efficient process for Cu interconnects [2, 3]. Compared with vacuum deposition processes, electroplated Cu provides improved super filling capabilities and abnormal grain growth phenomena. These properties contribute significantly to improved reliability of Cu interconnects. With the proper choice of additives and plating conditions, void-free, seam-free Damascene deposits are obtained which eliminates surface-like fast diffusion paths for Cu electromigration.