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© 2008 Springer-Verlag US
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Mohanty, S.P., Ranganathan, N., Kougianos, E., Patra, P. (2008). Power Modeling and Estimation at Transistor and Logic Gate Levels. In: Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76474-0_3
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DOI: https://doi.org/10.1007/978-0-387-76474-0_3
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