Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
A.J. Martin, S.M. Burns, T.K. Lee, D. Borkovic and P.J. Hazewindus, “The Design of an Asynchronous Microprocessor”, ARVLSI: Decennial Caltech Conference on VLSI, ed. C.L. Seitz, MIT Press, 1989, pp. 351–373.
S.B. Furber, P. Day, J.D. Garside, N.C. Paver and J.V. Woods, “AMULET1: A Micropipelined ARM”, Proceedings of CompCon'94, IEEE Computer Society Press, San Francisco, March 1994, pp.476–485.
A. Takamura, M. Kuwako, M. Imai, T. Fujii, M. Ozawa, I. Fukasaku, Y. Ueno and T. Nanya, “TITAC-2: A 32-Bit Asynchronous Microprocessor Based on Scalable-Delay-Insensitive Model”, Proceedings of ICCD'97, October 1997, pp. 288–294.
M. Renaudin, P. Vivet and F. Robin, “ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor”, Proceedings of Async'98, IEEE Computer Society, 1998, pp. 22–31. ISBN:0-8186-8392-9.
S.B. Furber, J.D. Garside and D.A. Gilbert, “AMULET3: A High-Performance Self-Timed ARM Microprocessor”, Proceedings of ICCD'98, Austin, TX, 5–7 October 1998, pp. 247–252. ISBN 0-8186-9099-2.
S.B. Furber, A. Efthymiou, J.D. Garside, M.J.G. Lewis, D.W. Lloyd and S. Temple, “Power Management in the AMULET Microprocessors”, IEEE Design and Test of Computers, ed. E. Macii, March–April 2001, Vol. 18, No. 2, pp. 42–52. ISSN: 0740-7475.
H. van Gageldonk, K. van Berkel, A. Peeters, D. Baumann, D. Gloor and G. Stegmann, “An Asynchronous Low-Power 80C51 Microcontroller”, Proceedings of Async'98, IEEE Computer Society, 1998, pp. 96–107. ISBN:0-8186-8392-9.
A. Bink and R. York, “ARM996HS: The First Licensable, Clockless 32-Bit Processor Core”, IEEE Micro, March 2007, Vol. 27, No. 2, pp. 58–68. ISSN: 0272-1732.
I. Sutherland, “Micropipelines”, Communications of the ACM, June 1989, Vol. 32, No. 6, pp.720–738. ISSN: 0001-0782.
J. Sparsø and S. Furber (eds.), “Principles of Asynchronous Circuit Design – A Systems Perspective”, Kluwer Academic Publishers, 2002. ISBN-10: 0792376137 ISBN-13: 978-0792376132.
S.B. Furber, D.A. Edwards and J.D. Garside, “AMULET3: A 100 MIPS Asynchronous Embedded Processor”, Proceedings of ICCD'00, 17–20 September 2000.
D. Seal (ed.), “ARM Architecture Reference Manual (Second Edition)”, Addison-Wesley, 2000. ISBN-10: 0201737191 ISBN-13: 978-0201737196.
J.D. Garside, “A CMOS VLSI Implementation of an Asynchronous ALU”,“Asynchronous Design Methodologies”, eds. S.B. Furber and M. Edwards, Elsevier 1993, IFIP Trans. A-28, pp. 181–207.
D. Hormdee and J.D. Garside, “AMULET3i Cache Architecture”, Proceedings of Async’01, IEEE Computer Society Press, March 2001, pp. 152–161. ISSN 1522-8681 ISBN 0-7695-1034-4.
W.A. Clark, “Macromodular Computer Systems”, Proceedings of the Spring Joint Conference, AFIPS, April 1967.
D.M. Chapiro, “Globally-Asynchronous Locally-Synchronous Systems”, Ph.D. thesis, Stanford University, USA, October 1984.
M. Lewis, J.D. Garside and L.E.M. Brackenbury, “Reconfigurable Latch Controllers for Low Power Asynchronous Circuits”, Proceedings of Async'99, IEEE Computer Society Press, April 1999, pp. 27–35.
A. Efthymiou, “Asynchronous Techniques for Power-Adaptive Processing”, Ph.D. thesis, Department of Computer Science, University of Manchester, UK, 2002.
A. Efthymiou and J.D. Garside, “Adaptive Pipeline Depth Control for Processor Power-Management”, Proceedings of ICCD'02, Freiburg, September 2002, pp. 454–457. ISBN 0-7695 1700-5 ISSN 1063-6404.
A. Efthymiou and J.D. Garside, “Adaptive Pipeline Structures for Speculation Control”, Proceedings of Async'03, Vancouver, May 2003, pp. 46–55. ISBN 0-7695-1898-2 ISSN 1522-8681.
W.S. Coates, J.K. Lexau, I.W. Jones, S.M. Fairbanks and I.E. Sutherland, “FLEETzero: An Asynchronous Switching Experiment”, Proceedings of Async'01, IEEE Computer Society, 2001, pp. 173–182. ISBN:0-7695-1034-5.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2008 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Furber, S., Garside, J. (2008). Temporal Adaptation – Asynchronicity in Processor Design. In: Wang, A., Naffziger, S. (eds) Adaptive Techniques for Dynamic Processor Optimization. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76472-6_10
Download citation
DOI: https://doi.org/10.1007/978-0-387-76472-6_10
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-76471-9
Online ISBN: 978-0-387-76472-6
eBook Packages: EngineeringEngineering (R0)