Scaling the supply voltage (Vdd) and threshold voltages (Vth) to an optimal point for a design can provide substantial power savings, particularly at a relaxed performance constraint. We will examine how Vdd, Vth and gate size affect the circuit delay, dynamic power and leakage power with analytical models. We compare these models to empirical fits for a 0.13um library characterized at different Vdd and Vth values. These models help us examine the trade-off between power and delay, and determine which power reduction techniques can provide the most benefit in different situations. In this chapter, we focus on use of a single supply voltage (Vdd) and a single threshold voltage (Vth). In Chapter 7, we will examine use of multiple supply and multiple threshold voltages in comparison to using a single Vdd and single Vth. Throughout this chapter, we assume that the NMOS and PMOS threshold voltages are of about the same magnitude, Vthn = –Vthp, and will generally refer to this value as the threshold voltage.
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Chinnery, D., Keutzer, K. (2007). Voltage Scaling. In: Closing the Power Gap Between ASIC & Custom. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68953-1_4
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