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High-Performance Computing and Networking

Volume 1067 of the series Lecture Notes in Computer Science pp 454-459

Date:

A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits

  • Fulvio CornoAffiliated withDip. di Automatica e Informatica, Politecnico di Torino
  • , Paolo PrinettoAffiliated withDip. di Automatica e Informatica, Politecnico di Torino
  • , Maurizio RebaudengoAffiliated withDip. di Automatica e Informatica, Politecnico di Torino
  • , Matteo Sonza ReordaAffiliated withDip. di Automatica e Informatica, Politecnico di Torino

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Abstract

The paper deals with the problem of Automatic Generation of Test Sequences for digital circuits. Genetic Algorithms have been successfully proposed to solve this industrially critical problem; however, they have some drawbacks, e.g., they are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using some of the standard benchmark circuits. The results show that it is able to significantly improve the results quality (by testing some critical faults) at the expense of increased CPU time requirements.