Lecture Notes in Computer Science Volume 1046, 1996, pp 193-204
Date: 07 Jun 2005

On word-level parallelism in fault-tolerant computing

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In this paper we present several simulations of operational PRAM on PRAM with memory or processor faults. Their common property is that they rely on the ability of performing standard boolean or arithmetic operations on words consisting of many bits.

The author would like to thank to Bogdan Chlebus, Suresh Venkatasubramanian and the anonymous referees, who helped to improve the readability of this paper.