Date: 31 May 2005

Multipliers and dividers: Insights on arithmetic circuit verification (extended abstract)

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Abstract

We consider methods for verifying multiplier and divider circuits based on symbolic function representations. Verification can be performed at either the bit-level, where individual signals are represented as Boolean functions, or at the word-level, where signal vectors are represented as “pseudo-Boolean” functions mapping Boolean variables to numeric values. These two classes of functions can be represented and manipulated as ordered Binary Decision Diagrams (BDDs), and Binary Moment Diagrams (BMDs), respectively.

It is impractical to verify multiplier or divider circuits entirely at the bit-level, because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using BDDs. Such analysis can be helpful when implementing complex arithmetic algorithms. As a demonstration, we show that Intel could have used BDDs to detect and even correct erroneous table entries in the Pentium floating point divider.

Abstracting to a word level offers two advantages over bit-level verification. First, it allows much more abstract and concise specifications in terms of arithmetic expressions. Second, we can verify complete multiplier circuits in polynomial time. Future extensions promise to enable word-level verification of divider circuits, as well.

This research is sponsored by the Wright Laboratory, Aeronautical Systems Center, Air Force Materiel Command, USAF, and the Advanced Research Projects Agency (ARPA) under grant number F33615-93-1-1330.