A Decade of Concurrency Reflections and Perspectives
Volume 803 of the series Lecture Notes in Computer Science pp 124175
Verification tools for finitestate concurrent systems
 E. ClarkeAffiliated withCarnegie Mellon
 , O. GrumbergAffiliated withThe Technion
 , D. LongAffiliated withAT&T Bell Labs
Abstract
Temporal logic model checking is an automatic technique for verifying finitestate concurrent systems. Specifications are expressed in a propositional temporal logic, and the concurrent system is modeled as a statetransition graph. An efficient search procedure is used to determine whether or not the statetransition graph satisfies the specification. When the technique was first developed ten years ago, it was only possible to handle concurrent systems with a few thousand states. In the last few years, however, the size of the concurrent systems that can be handled has increased dramatically. By representing transition relations and sets of states implicitly using binary decision diagrams, it is now possible to check concurrent systems with more than 10^{120} states. In this paper we describe in detail how the new implementation works and give realistic examples to illustrate its power. We also discuss a number of directions for future research. The necessary background information on binary decision diagrams, temporal logic, and model checking has been included in order to make the exposition as selfcontained as possible.
Keywords
automatic verification temporal logic model checking binary decision diagrams Title
 Verification tools for finitestate concurrent systems
 Book Title
 A Decade of Concurrency Reflections and Perspectives
 Book Subtitle
 REX School/Symposium Noordwijkerhout, The Netherlands June 1–4, 1993 Proceedings
 Pages
 pp 124175
 Copyright
 1994
 DOI
 10.1007/3540580433_19
 Print ISBN
 9783540580430
 Online ISBN
 9783540484233
 Series Title
 Lecture Notes in Computer Science
 Series Volume
 803
 Series ISSN
 03029743
 Publisher
 Springer Berlin Heidelberg
 Copyright Holder
 SpringerVerlag
 Additional Links
 Topics
 Keywords

 automatic verification
 temporal logic
 model checking
 binary decision diagrams
 Industry Sectors
 eBook Packages
 Editors
 Authors

 E. Clarke ^{(1)}
 O. Grumberg ^{(2)}
 D. Long ^{(3)}
 Author Affiliations

 1. Carnegie Mellon, Pittsburgh
 2. The Technion, Haifa
 3. AT&T Bell Labs, Murray Hill
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