Abstract
Cost-effective parallel hardware for performing pattern directed (i.e. associative) search, transitive closure, etc., is becoming a reality. It is therefore appropriate to re-examine classical computational models for logic programming, to see whether the power offered by this new hardware can be exploited. We describe two computational models. One supports parallelism (AND-parallelism and OR-parallelism) by replacing a WAM stack-based configuration by associative memory; this is a direct consequence of using fixpoint computations instead of the traditional resolution rule principle. The other exploits the potential of parallelisms in logic programs (especially unification parallelism and the pipeline parallelism between inference and unification) with the idea of separating unification from inference, as proposed in the field of Theorem Proving. Both these approaches produce requirements for tasks which could be performed by special hardware. We comment on the prospects for implementing such hardware, based on our experience of a SIMD parallel associative memory which also offers a range of set and graph operations.
Jiwei Wang is moving to the Department of Computer Science, University of Bristol, Bristol BS8 1TR
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Wang, J., Marsh, A., Lavington, S. (1992). Non-WAM models of logic programming and their support by novel parallel hardware. In: Fronhöfer, B., Wrightson, G. (eds) Parallelization in Inference Systems. Lecture Notes in Computer Science, vol 590. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55425-4_13
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DOI: https://doi.org/10.1007/3-540-55425-4_13
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