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International Work-Conference on Artificial Neural Networks

IWANN 2003: Artificial Neural Nets Problem Solving Methods pp 41–48Cite as

A Binary Multiplier Using RTD Based Threshold Logic Gates

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2687))

Abstract

A binary multiplier implemented using RTD based threshold logic gates is presented. The circuit demonstrates how small-scale threshold logic gates implementing standard boolean functions can be used to replace conventional boolean gates and achieve reduced circuit complexity. The performance of the gates and multiplier are simulated in HSPICE and the results are presented.

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References

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Author information

Authors and Affiliations

  1. Intelligent Systems Engineering Laboratory, Faculty of Informatics, University of Ulster, Derry, BT48 7JL, Northern Ireland, UK

    P M Kelly, C J Thompson, T M McGinnity & L P Maguire

Authors
  1. P M Kelly
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  2. C J Thompson
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  3. T M McGinnity
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  4. L P Maguire
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Editor information

Editors and Affiliations

  1. E.T.S. de Ingeniería Informática Departamento de Inteligencia Artificial, Universidad Nacional de Educación a Distancia, Juan del Rosal, 16, 28040, Madrid, Spain

    José Mira  & José R. Álvarez  & 

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© 2003 Springer-Verlag Berlin Heidelberg

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Kelly, P.M., Thompson, C.J., McGinnity, T.M., Maguire, L.P. (2003). A Binary Multiplier Using RTD Based Threshold Logic Gates. In: Mira, J., Álvarez, J.R. (eds) Artificial Neural Nets Problem Solving Methods. IWANN 2003. Lecture Notes in Computer Science, vol 2687. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44869-1_6

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  • DOI: https://doi.org/10.1007/3-540-44869-1_6

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40211-4

  • Online ISBN: 978-3-540-44869-3

  • eBook Packages: Springer Book Archive

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