Abstract
The Open Research Compiler (ORC), jointly developed by Intel Microprocessor Technology Labs and the Institute of Computing Technology at Chinese Academy of Sciences, has become the leading open source compiler on the ItaniumTM Processor Family (IPF, previously known as IA-64). Since its first release in 2002, it has been widely used in academia and industry worldwide as a compiler and architecture research infrastructure and as code base for further development. In this paper, we present an overview of the design of the major components in ORC, especially those new features in the code generator. We discuss the development methodology that is important to achieving the objectives of ORC. Performance comparisons with other IPF compilers and a brief summary of the research work based on ORC are also presented.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ball, T., Larus, J.: Optimally profiling and tracing programs. ACM Transactions on Programming Languages and Systems 16(3), 1319–1360 (1994)
Ball, T., Larus, J.: Efficient path profiling. In: Proc. 29th Annual Intl. Symp. on Microarchitecture (December 1996)
Berkeley Unified Parallel C (UPC) Project, http://upc.lbl.gov
Berstein, D., Rodeh, M.: Global Instruction Scheduling for Superscalar Machines. In: Proc. of SIGPLAN 1991 Conference on Programming Language Design and Implementation (1991)
Calder, B., Feller, P., Eustance, A.: Value Profiling. In: Proc. 30th Annual Intl. Symp. on Microarchitecture (December 1997)
Chen, D., Liu, L., Fu, C., Yang, S., Wu, C., Ju, R.: Efficient Resource Management during Instruction Scheduling for the EPIC Architecture. In: Proc. of the 12th International Conference on Parallel Architectures and Compilation Techniques, New Orleans (September 2003)
Chow, F., Chan, S., Kennedy, R., Liu, S., Lo, R., Tu, P.: A New Algorithm for Partial Redundancy Elimination Based on SSA Form. In: Proc. of SIGPLAN 1997 Conf. on Programming Language Design and Implementation (May 1997)
Chow, F., Lo, R., Liu, S., Chan, S., Streich, M.: Effective Representation of Aliases and Indirect Memory Operations in SSA Form. In: Proc. of 6th Int’l Conf. on Compiler Construction (April 1996)
Du, Z., Lim, C., Li, X., Yang, C., Zhao, Q., Ngai, T.: A Cost-Driven Compilation Framework for Speculative Parallelization of Sequential Programs. In: Proc. of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation (2004)
Eichenberger, A., Davidson, E.: Register allocation for predicated code. In: Proc. of the 28th Annual International Symposium on Microarchitecture (December 1995)
Faraboschi, P., Fisher, J., Young, C.: Instruction Scheduling for Instruction Level Parallel Processors. Proceedings of the IEEEÂ 89(11) (November 2001)
Fisher, J.: Trace scheduling: A Technique for Global Microcode Compaction. IEEE Trans. on Computers 7 (1981)
Gao, G., Amaral, J., Dehnert, J., Towle, R.: The SGI Pro64 Compiler Infrastructure. In: 2000 International Conference on Parallel Architectures and Compilation Techniques, Tutorial (October 2000)
Hank, R.: Region Based Compilation, Doctoral thesis, University of Illinois at Urbana Champaign (1996)
Havanki, W.: Treegion Scheduling for VLIW Processors, MS Thesis, Dept.of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC (1997)
University of Houston, Dragon Analysis Tool, http://www2.cs.uh.edu/~dragon
Hwu, W., Mahlke, S., Chen, W., Chang, P., Warter, N., Bringmann, R., Ouellette, R., Hank, R., Kiyohara, T., Haab, G., Holm, J., Lavery, D.: The Superblock: An Effective Technique for VLIW and Superscalar Compilation. Journal of Supercomputing 7(1,2), 229–248 (1993)
Intel, Intel Itanium Architecture Software Developer’s Manual, ?vol. 1 (October 2002)
Intel, Itanium Processor Microarchitecture Reference (March 2000)
Intel, Itanium Microarchitecture Knobs API Programmer’s Guide (2001)
Intel, ICT.: The Open Research Compiler Project, http://ipf-orc.sourceforge.net
Johnson, R., Schlansker, M.: Analysis technique for predicated code. In: Proceedings of the 29th International Symposium on Microarchitecture (December 1996)
Ju, R., Chan, S., Ngai, T., Wu, C., Lu, Y., Zhang, J.: Open Research Compiler (ORC) 2.0 and Tuning Performance on Itanium, Micro-35 Tutorial, Istanbul, Turkey, November 19 (2002)
Ju, R., Nomura, K., Mahadevan, U., Wu, L.: A Unified Compiler Framework for Control and Data Speculation. In: 2000 International Conference on Parallel Architectures and Compilation Techniques (October 2000)
Kennedy, R., Chan, S., Liu, S., Lo, R., Tu, P., Chow, F.: Partial Redundancy Elimination in SSA Form. TOPLASÂ 21(3) (May 1999)
Lin, J., Chen, T., Hsu, W., Yew, P., Ju, R., Ngai, T., Chan, S.: A Compiler Framework for Speculative Analysis and Optimizations. In: Proc. of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation (2003)
Liu, Y., Zhang, Z., Qiao, R., Ju, R.: A Region-Based Compilation Infrastructure. In: Proc. of the 7th Workshop on Interaction between Compilers and Computer Architectures (2003)
Lo, R., Chow, F., Kennedy, R., Liu, S., Tu, P.: Register Promotion by Sparse Partial Redundancy Elimination of Loads and Stores. In: Proc. of SIGPLAN 1998 Conf. on Programming Language Design and Implementation (June 1998)
Mahlke, S., Chen, W., Hwu, W., Rau, B., Schlansker, M.: Sentinel Scheduling for Superscalar and VLIW Processors. In: Proc. of the 5th Int’l Conference on Ar-chitectural Support for Programming Languages and Operating Systems (October 1992)
Mahlke, S., Lin, D., Chen, W., Hank, R., Bringmann, R.: Effective Compiler Support for Predicted Execution Using the Hyperblock. In: Proceedings of 25th international symposium of Microarchitecture (1992)
Rice University, Open64 Project, http://www.hipersoft.rice.edu/open64
SGI.: WHIRL Intermediate Language Specification, http://open64.sourceforge.net
SGI, Standard Template Library Programmer’s Guide, http://www.sgi.com/tech/stl
Tsinghua University, ORC-OpenMP Project, http://sourceforge.net/projects/orc-openmp
Wolf, M., Maydan, D., Chen, D.: Combining Loop Transformations Considering Caches and Scheduling. In: MICRO-29 (December 1996)
Wu, Y.: Efficient Discovery of Regular Stride Patterns In Irregular Programs and Its Use in Compiler Prefetching. In: PLDI 2002, Berlin, Germany (June 2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Wu, C. et al. (2005). An Overview of the Open Research Compiler. In: Eigenmann, R., Li, Z., Midkiff, S.P. (eds) Languages and Compilers for High Performance Computing. LCPC 2004. Lecture Notes in Computer Science, vol 3602. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11532378_3
Download citation
DOI: https://doi.org/10.1007/11532378_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-28009-5
Online ISBN: 978-3-540-31813-2
eBook Packages: Computer ScienceComputer Science (R0)