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Test Pattern Generation and Fault Simulation

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Abstract

Structural test programs are used in production test in order to reduce the time taken to test the fabricated IC when compared to an exhaustive functional test. Structural tests are based on the development of test vectors to detect specific faults that are considered to exist in a circuit due to process defects. The generation of the necessary test vectors is undertaken using test pattern generation and fault simulation techniques and tools.

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10.10 References

  1. Bushnell M. and Agrawal V., “Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers, 2000, ISBN 0-7923-7991-8

    Google Scholar 

  2. Hurst S., “VLSI Testing digital and mixed analogue/digital techniques”, IEE, 1998, ISBN 0-85296-901-5

    Google Scholar 

  3. Zwolinski M., “Digital System Design with VHDL”, Pearson Education Limited, 2000, England, ISBN 0-201-36063

    Google Scholar 

  4. IEEE Std 1076-2002, IEEE Standard VHDL Language Reference Manual, IEEE, USA

    Google Scholar 

  5. IEEE 1364-1995, IEEE Standard Verilog® Hardware Description Language, IEEE, USA

    Google Scholar 

  6. TetraMAX® ATPG, Synopsys Inc., USA

    Google Scholar 

  7. Synopsys Inc., USA, http://www.synopsys.com

    Google Scholar 

  8. DFT Compiler®, Synopsys Inc., USA

    Google Scholar 

  9. Miara A. and Giambiasi N., “Dynamic and deductive fault simulation”, Proceedings of the 15th conference on Design Automation Conference, USA, 1978, pp439–443

    Google Scholar 

  10. Verifault-XL® Fault Simulator User Guide, Cadence Design Systems Inc., USA

    Google Scholar 

  11. Cadence Design Systems Inc., USA, http:://www.cadence.com

    Google Scholar 

  12. Verilog-XL® User Guide, Cadence Design Systems Inc., USA

    Google Scholar 

  13. Grout I., “An Analogue and Mixed-Signal Fault Simulation Tool based on Tcl/Tk and HSpice”, Proceedings of the Iberchip 2002 Workshop, Mexico, 2002

    Google Scholar 

  14. “Antics Analogue Fault Simulation Software”, University of Hull, UK, http://www.eng.hull.ac.uk/research/ee_vlsi/antics.htm

    Google Scholar 

  15. Mir S. et al., “SWITTEST: Automatic Switch-level Fault Simulation and Test Evaluation of Switched-Capacitor Systems2, Proceedings of the 34th Design Automation Conference, 1997, pp281–286

    Google Scholar 

  16. Straube B., Vermeiren W., Müller B., “Using an Analogue Fault Simulator for Microsystem Fault Simulation”, Proceedings of the 4th IEEE International Mixed Signal Testing Workshop, The Netherlands, 1998

    Google Scholar 

  17. Olbrich T. et al, “A New Quality Estimation Methodology for Mixed-Signal and Analogue ICs”, Proceedings of the European Design & Test Conference, France, 1997, pp573–580

    Google Scholar 

  18. Olbrich T. et al., “Defect-Oriented Vs Schematic-Level Based Fault Simulation for Mixed-Signal ICs”, Proceedings of International Test Conference USA, 1996, pp 511–520

    Google Scholar 

  19. Walker H. and Stephen W., “VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits”, IEEE Transactions on Computer-Aided Design, Vol.CAD-5, No. 4, October 1986, pp541–556

    Google Scholar 

  20. Ferguson F. and Shen J., “A CMOS Fault Extractor for Inductive Fault Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 7, No. 11, November 1988, pp1181–1194

    Article  Google Scholar 

  21. Hawkins C. Soden J., Righter A. and Ferguson F., “Defect Classes — An Overdue Paradigm for CMOS IC Testing”, Proceedings of International Test Conference, USA, 1994, pp 413–425

    Google Scholar 

  22. Hawkins C. and Segura J., “Failure Modes in Nanometer Technologies”, Tutorial D2, Design and Automation in Europe Conference (DATE), 2003

    Google Scholar 

  23. Gaitonde D. and Walker D., “Hierarchical Mapping of Spot Defects to Catastrophic Faults — Design and Applications”, IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No. 2, May 1995, pp167–177

    Article  Google Scholar 

  24. Chess B., Roth C. and Larrabee T., “On Evaluating Competing Bridge Fault Models for CMOS ICs”, Proceedings of the 12th IEEE VLSI Test Symposium, 1994, pp446–451

    Google Scholar 

  25. MacMillen D. et al., “An Industrial View of Electronic Design Automation”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 19, No. 12, December 2000, pp1428–1448

    Article  Google Scholar 

  26. IEEE standard VHDL analog and mixed-signal extensions, Std 1076.1-1999, IEEE, USA

    Google Scholar 

  27. Open Verilog International (OVI), Verilog Analog Mixed-Signal Group, http://www.eda.org/verilog-ams/

    Google Scholar 

  28. Fang L., Kerkhoff H. and Gronthoud G., “Reducing Analogue Fault-Simulation Time by Using High-Level Modelling in Dotss for an Industrial Design”, Proceedings of the IEEE European Test Workshop (ETW’01), 2001, pp61–67

    Google Scholar 

  29. Kilic Y. and Zwolinski M., “Speed-up Techniques for Fault-based Analogue Fault Simulation”, Proceedings of the European Test Workshop, 2001

    Google Scholar 

  30. Perkins A. et al., “Fault Modeling And Simulation Using VHDL-AMS”, Analog Integrated Circuits and Signal Processing, Vol. 16, No. 2, 1998, pp141–155.

    Article  MathSciNet  Google Scholar 

  31. Grout I. and Santana J., “Mechatonic System Fault Simulation study with Spectre and Verilog-A”, Proceedings of the Mechatronics Forum Conference, The Netherlands, 2002

    Google Scholar 

  32. Soma M. et al., “Hierarchical ATPG for Analog Circuits and Systems”, IEEE Design and Test of Computers, January–February 2001, pp72–81

    Google Scholar 

  33. Godambe N. and Shi C., “Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults using VHDL-AMS”, Proceedings of the 15th IEEE VLSI Test Symposium, 1997, pp177–182

    Google Scholar 

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© 2006 Springer-Verlag London Limited

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(2006). Test Pattern Generation and Fault Simulation. In: Integrated Circuit Test Engineering. Springer, London. https://doi.org/10.1007/1-84628-173-3_10

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  • DOI: https://doi.org/10.1007/1-84628-173-3_10

  • Publisher Name: Springer, London

  • Print ISBN: 978-1-84628-023-8

  • Online ISBN: 978-1-84628-173-0

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