Abstract
Reconfigurable hardware will be used in many future embedded applications. Since most of these embedded systems will be temporarily or permanently connected to a network, the possibility to reload parts of the application at run time arises. In the 90ies it was recognized, that a huge variety of processors would lead to a tremendous amount of binaries for the same piece of software. For the hardware parts of an embedded system, the situation today is even worse. The java approach based on a java virtual machine (JVM) was invented to solve the problem for software. In this paper, we show how the hardware parts of an embedded system can be implemented in a hardware byte code, which can be interpreted using a virtual hardware machine running on an arbitrary FPGA. Our results show that this approach is feasible and that it leads to fast, portable and reconfigurable designs, which run on any programmable target architecture.
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Lange, S., Kebschull, U. (2005). Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems. In: Lysaght, P., Rosenstiel, W. (eds) New Algorithms, Architectures and Applications for Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-3128-9_11
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DOI: https://doi.org/10.1007/1-4020-3128-9_11
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-3127-4
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