Summary
Model your clock signals in a module. Be careful about time resolution issues, delta cycle alignment and implicit synchronization of asynchronous signals.
Encapsulate repetitive physical-level operations into bus-functional tasks. Collect all of the bus-functional tasks for a physical interface or protocol into a bus-functional model. Detect concurrent activation of bus-functional tasks within the same bus-functional model using a semaphore.
Design an effective transaction-level interface with a suitable transaction completion and status notification mechanism.
Provide callbacks in bus-functional models and response monitors to enable access to symbol-level protocol parameters and inject symbol-level errors.
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© 2006 Springer Science+Business Media, Inc.
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Bergeron, J. (2006). Stimulus and Response. In: Writing Testbenches using System Verilog. Springer, Boston, MA. https://doi.org/10.1007/0-387-31275-7_5
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DOI: https://doi.org/10.1007/0-387-31275-7_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-29221-2
Online ISBN: 978-0-387-31275-0
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