IN this chapter, a specific case of timing errors will be analyzed in detail from a functional point of view. This error concerns relative timing inaccuracies. The functional and some architectural issues of this error raised in chapter 5.2.5 will be addressed. Here the focus is on the DAC core hardware in relation to the properties of the errors and their relationship with the architectural parameters. The input signals are assumed sinusoidal.
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© 2006 Springer
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(2006). Functional analysis of local timing errors. In: Wide-Bandwidth High-Dynamic Range D/A Converters. The International Series in Engineering and Computer Science, vol 871. Springer, Boston, MA. https://doi.org/10.1007/0-387-30416-9_08
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DOI: https://doi.org/10.1007/0-387-30416-9_08
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-30415-1
Online ISBN: 978-0-387-30416-8
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