Abstract
In this chapter we begin with an overview of thermal modeling of high performance microprocessors with emphasis on the necessity of these models to ensure a reliable system. Later in this chapter we review the concept of the electro-thermal modeling and describe several approaches to electro-thermal modeling at architecture and circuit levels.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Databook “Leistungshalbleiter” (02.97), Siemens AG, S. 1 15ff.
M. Marz, P. Nance, “Thermal Modeling of Power-electronic Systems”, Infineon Technologies, AG, Munich.
W. Wondrak, “Physical limits and lifetime limitations of semiconductor devices at high temperature”. Microelectronics Reliability, Vol. 39 No. 6–7, pages 1113–1120, 1999.
International Technology Roadmap for Semiconductors (ITRS). http://public.itrs.net.
H. Sanchez, B. Kuttanna, T. Olson, M. Alexander, G. Gerosa, R. Philip, and J. Alvarez. “Thermal management system for high performance PowerPC microprocessors”. Proceedings of IEEE COMPCON, pages 325–330, 1997.
G. Gerosa, M. Alexander, J. Alvarez, C. Croxton, M. D’Addeo, A.R. Kennedy, C. Nicoletta, J.P. Nissen, R. Philip, P. Reed, H. Sanchez, S.A. Taylor, and B. Burgess, “A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cash controller”. IEEE Journal of Solid-state Circuits, Vol. 32, No. 11, pages 1635–1649, 1997.
L. Geiling, “ Über die elektrische Nachbildung von Wärmeleitungsvorgängen”, Siemens Zeitschrift 35, pages 98–104, 1961.
D. Brooks and M. Martonosi, “Dynamic thermal management for highperformance microprocessors”, In Proceedings of the Seventh International Symposium On High-Performance Computer Architecture, pages 171–82, 2001.
W. Huang, J. Renau, S.-M. Yoo, and J. Torellas, “A framework for dynamic energy efficiency and temperature management”, In Proceedings Of the 33rd Annual IEEEIACM International Symposium on Microarchitecture, pages 202–213, 2000.
K. Skadron, T. Abdelzaher, and M. R. Stan, “Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management”, In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pages 17–28, 2002.
K. Skadrony, M. Stanz, M. Barcellaz, A. Dwarkaz, W. Huangz, Y. Liy, Y. Maz, A. Naiduy, D. Parikhy, P. Rez, G. Rosez, K. Sankaranarayanany, R. Suryanarayanz, S. Velusamyy, H. Zhangz, Y. Zhangz, “HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level”, 8th THERMINIC Workshop, pages 1–4 2002.
M. Matson “Circuit implementation of a 600MHZ superscalar RISC microprocessor. Computer Design”, VLSI in Computers and Processors, Vol. 26, No. 2, pages 104–110, 1998.
S. Lee, S. Song, V. Au, K. Moran, “Constricting/Spreading resistance model for electronics packaging”, proceedings of AJTEC, pages 199–206, 1995.
K. Skadron, “Temaperature aware micro-architecture: extended discussion and results” Technical report, CS-2003-08, University of Virginia, Department of Computer Science, 2003.
Y-K. Cheng, E. Rosenbaum, S-M. Kang, “ETS-A: A New Electro-thermal Simulator for CMOS VLSI Circuits”, In Proceedings of ED&TC’96, pages 566–570, 1996.
Y-K. Cheng, Ch-Ch. Teng, A. Dharchoudhury, E. Rosenbaum, S-M. Kang, “iCET: A complete chip-level thermal reliability diagnosis tool for CMOS VLSI”, In Proceedings of ICCAD’96, pages 548–551, 1996.
V. Sz’ekely, A. Poppe, A. P’ahi, A. Csendes, and G. Hajas, “Electrothermal and logi-thermal simulation of VLSI designs”, IEEE Transaction On VLSI Systems, Vol. 5, No. 3, pages 258–69, 1997.
V. Székely, “THERMODEL: a tool for compact dynamic thermal model generation”, Proceedings of the 2nd THERMINIC Workshop, pages 21–26, 1996.
V. Székely, “Identification of RC Networks by Deconvolution: Chances and Limits”, IEEE Transactions on Circuits and Systems-I. Theory and applications, Vol. 45, No. 3, pages 244–258, 1998.
V. Székely, “SUNRED: a new thermal simulator and typical applications”, Proceedings of the 3rd THERMINIC Workshop, pages 84–90, 1997.
M. Rencz, V. Székely, “A generic method for thermal multiport model generation of IC packages”, Proceedings of SEMI-THERM pages 145–152, 2001.
V. Székely, K. Tarnay, “Accurate algorithm for temperature calculation in nonlinear circuit analysis”, Electronics Letters, Vo1.8, No. 19, pages 470–472, 1972.
K. Nemeth, “On the Analysis of Nonlinear Networks Considering the Effect of Temperature”, IEEE Journal of Solid-state Circuits, SC-Vol. 11, No. 8, pages 550–552, 1976.
K. Fukahori, P.R. Gray, “Computer simulation of integrated circuits in the presence of electro-thermal interaction”, IEEE Journal of Solid-state Circuits, SC-Vol. 11, No. 12, pages 834–846, 1976.
V. Székely, “Accurate calculation of device heat dynamics: a special feature of the TRANS-TRAN circuit analysis program”, Electronics Letters, Vol. 9, No. 6, pages 132–134, 1973.
W.V. Petegem, B. Geeraerts, W. Sansen, B. Graindourze, “Electrothermal simulation and design of integrated circuits”, IEEE Journal of Solid-State Circuits, SSC-Vol. 29, No. 2, pages 143, 1994.
W.H. Kao, W.K. Chu, “ATLAS: An Integrated Thermal Layout and Simulation System of ICs”, In Proceedings of ED&TC’94, 1994.
S. Lee, D.J. Allstot, “Electrothermal simulation of integrated circuits”, IEEE Journal of Solid-State Circuits, SSC-Vol. 28, No. 12, pages 1283–1293, 1993.
S. Wunsche, C. Clauss, P. Schwarz, F. Winkler, “Electrothermal circuit simulation using simulator coupling”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 5, Issue 3, Pages: 277–282, 1997.
W. van Petegem, B. Geeraerts, W. Sansen, B. Graindourze, “Electrothermal simulation and design of integrated circuits”, IEEE Journal of Solid-State Circuits, Volume 29, Issue 2, Pages 143–146, 1994.
C.C. Lee, A.L. Palisoc, J.M.W. Baynham, “Thermal analysis of solid-state devices using the boundary element method”, IEEE Transactions on Electron Devices, Volume 35, Issue 7, Pages 1151–1153, 1988.
K. Fukahori, P.R. Gray, “Computer simulation of integrated circuits in the presence of electrothermal interaction”, IEEE Journal of Solid-State Circuits, Volume 11, Issue 6, Pages 834–846, 1976.
G. Digele, S. Lindenkreuz,; E. Kasper, “Fully coupled dynamic electrothermal simulation”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 5, Issue 3, Pages 250–257, 1997.
M. Latif, P.R. Bryant, “Network Analysis Approach to Multidimensional Modeling of Transistors Including Thermal Effects”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 1, Issue 2, Pages 94–101, 1982.
A. Haji-Sheikh, “Peak temperature in high-power chips”, IEEE Transactions on Electron Devices, Volume 37, Issue 4, Pages 902–907, 1990.
X. Gui, G.-B. Gao, H. Morkoc, “Simulation study of peak junction temperature and power limitation of AlGaAs/GaAs HBTs under pulsed and CW operation”, IEEE Electron Device Letters, Volume 13, Issue 8, Pages 411–413, 1992.
K. Chang-Woo, N. Goto, K. Honjo, “Thermal behavior depending on emitter finger and substrate configurations in power heterojunction bipolar transistors”, IEEE Transactions on Electron Devices, Volume 45, Issue 6, Pages 1190–1195, 1998.
L.L. Liou, B. Bayraktaroglu, “Thermal stability analysis of AlGaAs/GaAs heterojunction bipolar transistors with multiple emitter fingers”, IEEE Transactions on Electron Devices, Volume 41, Issue 5, Pages 629–636, 1994.
L. Arthur, A.L. Palisoc, C. Lee Chin, “Exact thermal representation of multilayer rectangular structures by infinite plate structures using the method of images”, Journal of Applied Physics, Volume 64, Issue 12, pages 6851–6857, 1988.
N. Rinaldi, “Thermal analysis of solid-state devices and circuits: an analytical approach”, Journal of Solid State Electronics, Volume 44, pages 1789–1798, 2000.
DH. Smith, A. Fraser, and. J. ONeil, “Measurement and prediction of operating temperatures”, Proceedings of SEMITHERMIN Symposium, 1986.
A. Vassighi, A. Keshavarzi, S. Narendra, G. Schrom, Y. Ye, S. Lee, G. Chrysler, M. Sachdev, V. De, “Design optimizations for microprocessors at low temperature”, Proceedings of Design Automation Conference, pages 2–5, 2004.
K. Banerjee, L. Sheng-Chih, A. Keshavarzi, S. Narendra, and V. De, “A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management”, IEEE International Electron Devices Meeting, pages 36.7.1–36.7.4, 2003.
A. Vassighi, O. Semenov, and M. Sachdev, “Thermal Runaway Avoidance”, IEEE International Reliability Physics Symposium, pages 655–656, 2004.
S. Narendra, V. De, S. Borkar, D. A. Antoniadis, and A.P. Chandrakasan, “Full chip subthreshold leakage power prediction and reduction techniques for sub-0.18µm CMOS”, IEEE Journal of Solid-state Circuits, Vol. 39, No. 3, pages 501–510, 2004.
J. M. Rabaey. “Digital Integrated Circuits”, Prentice Hall, U.S.A, 1996.
S. M. Sze, “Physics of Semiconductor Device”, John Wiley & Sons, Inc., U.S.A, 1936.
Y. Taur, T.H. Ning, “Fundamentals of modem VLSI devices”, Cambridge, UK, Cambridge University Press, 1998.
Rights and permissions
Copyright information
© 2006 Springer Science+Business Media, Inc.
About this chapter
Cite this chapter
(2006). Thermal and Electrothermal Modeling. In: Thermal and Power Management of Integrated Circuits. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-29749-9_4
Download citation
DOI: https://doi.org/10.1007/0-387-29749-9_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-25762-4
Online ISBN: 978-0-387-29749-1
eBook Packages: EngineeringEngineering (R0)