Skip to main content

Delay Testing

  • Chapter
  • 1059 Accesses

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 27))

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. G. Moore, “Cramming More Components Onto Integrated Circuits”, Electronics, April 19, 1965, ftp://download.intel.com/research/silicon/moorespaper.pdf.

  2. “International Technology Roadmap For Semiconductors”, 2003 Edition, Semiconductor International Association, http://public.itrs.net/.

  3. A Krstic, J. Liou, Y. Jiang, K. Cheng, “Delay Testing Considering Crosstalk-Induced Effects”, Proceedings International Test Conference, pp. 558-567, Oct 2001.

    Google Scholar 

  4. S. Chakravarty, “On The Capability Of Delay Tests To Detect Bridges And Opens”, Proceedings 6th Asian Test Symposium, pp. 314-319, Nov 1997.

    Google Scholar 

  5. A. Pierzynska, S. Pilarski, “Pitfalls In Delay Fault Testing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 16, i. 3, pp. 321-329, March 1997.

    Article  Google Scholar 

  6. S. C. Ma, P. Franco, E. J. McCluskey, “An Experimental Chip To Evaluate Test Techniques Experiment Results”, International Proceedings Test Conference, pp. 663-672, Oct 1995.

    Google Scholar 

  7. J. Saxena, K. M. Butler, J. Gatt, R. Raghuraman, S. P. Kumar, S. Basu, D. J. Campbell, J. Berech, “Scan-Based Transition Fault Testing -Implementation And Low Cost Test Challenges”, Proceedings International Test Conference, pp. 1120-1129, Oct 2002.

    Google Scholar 

  8. P. C. Maxwell, R. C. Aitken, K. R. Kollitz, A. C. Brown, “IDDQ And AC Scan: The War Against Unmodelled Defects”, Proceedings International Test Conference, pp. 250-258, Oct 1996.

    Google Scholar 

  9. M. Renovell, J. M. Galliere, F. Azais, Y. Bertrand, “Delay Testing Of MOS Transistor With Gate Oxide Short”, Proceedings 12th Asian Test Symposium, pp. 168-173, Nov 2003.

    Google Scholar 

  10. R. Madge, B. R. Benware, W. R. Daasch, “Obtaining High Defect Coverage For Frequency-Dependent Defects In Complex ASICs”, IEEE Design & Test of Computers, v. 20, i. 5, pp. 46-53, Sept 2003.

    Article  Google Scholar 

  11. J. Liou, A. Krstic, Y. Jiang, K. Cheng, “Modeling, Testing, And Analysis For Delay Defects And Noise Effects In Deep Submicron Devices”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 22, i. 6, pp. 756-769, June 2003.

    Article  Google Scholar 

  12. S. F. Midkiff, W. Y. Koe, “Test Effectiveness Metrics For CMOS Faults”, Proceedings International Test Conference, pp. 653-659, Aug 1989.

    Google Scholar 

  13. R. David, S. Rahal, J. L. Rainard, “Some Relationships Between Delay Testing And Stuck-Open Testing In CMOS Circuits”, Proceedings of the European Design Automation Conference, pp. 339-343, March 1990.

    Google Scholar 

  14. P. Nigh, D. Vallett, A. Patel, J. Wright, F. Motika, D. Forlenza, R. Kurtulik, W. Chong, “Failure Analysis Of Timing And IDDq-Only Failures From The SEMATECH Test Methods Experiment”, Proceedings International Test Conference, pp. 1152-1161, Sept 1999.

    Google Scholar 

  15. K. Baker, G. Gronthoud, M. Lousberg, I. Schanstra, C. Hawkins, “Defect-Based Delay Testing Of Resistive Vias-Contacts A Critical Evaluation”, Proceedings International Test Conference, pp. 467-476, Sept 1999.

    Google Scholar 

  16. M. Sharma, J. H. Patel, “Enhanced Delay Defect Coverage With Path-Segments”, Proceedings International Test Conference, pp. 385-392, Oct 2000.

    Google Scholar 

  17. A. Krstic, K. Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Academic Publishers, Norwell, MA, 1998, ISBN: 0792382951.

    Google Scholar 

  18. S. Wang, X. Liu, S. T. Chakradhar, “Hybrid delay Scan: A Low Hardware Overhead Scan-based Delay Test Technique For High Fault Coverage And Compact Test Sets”, Proceedings Design, Automation and Test in Europe Conference and Exhibition, v. 2, pp. 1296-1301, Feb 2004.

    Google Scholar 

  19. J. Rearick, “Too Much Delay Fault Coverage Is A Bad Thing”, Proceedings International Test Conference, pp. 624-633, Oct 2001.

    Google Scholar 

  20. H. Li, Y. Zhang, X. Li, “Delay Test Pattern Generation Considering Crosstalk-Induced Effects”, Proceedings 12th Asian Test Symposium, pp. 178-183, Nov 2003.

    Google Scholar 

  21. A. Attarha, M. Nourani, “Test Pattern Generation for Signal Integrity Faults on Long Interconnects”, Proceedings 20th IEEE VLSI Test Symposium, pp. 336-341, April 2002.

    Google Scholar 

  22. J. Savir, S. Patil, “Scan-Based Transition Test”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 12, i. 8, pp. 1232-1241, Aug 1993.

    Article  Google Scholar 

  23. S. Ohtake, K. Ohtani, H. Fujiwara, “A Method Of Test Generation For Path Delay Faults Using Stuck-at Fault Test Generation Algorithms”, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp. 310-315, 2003.

    Google Scholar 

  24. M. Abadir, J. Zhu, “Transition Test Generation Using Replicate-and-Reduce Transform For Scan-based Designs”, Proceedings 21st IEEE VLSI Test Symposium, pp. 22-27, 2003.

    Google Scholar 

  25. B. R. Benware, R. Madge, C. Lu, R. Daasch, “Effectiveness Comparisons Of Outlier Screening Methods For Frequency Dependent Defects On Complex ASICs”, Proceedings 21st VLSI Test Symposium, pp. 39-46, April 2003.

    Google Scholar 

  26. B. D. Cory, R. Kapur, B. Underwood, “Speed Binning With Path Delay Test In 150-nm Technology”, IEEE Design & Test of Computers, v. 20, i. 5, pp. 41-45, Sept 2003.

    Article  Google Scholar 

  27. T. McLauren, “Debugging And Diagnosing Delay Defects In Deep Submicron Designs”, Silicon Debug and Diagnosis Conference, 2004.

    Google Scholar 

  28. E. S. Park, B. Underwood, T. W. Williams, M. R. Mercer, “Delay Testing Quality In Timing-Optimized Designs” Proceedings International Test Conference, pp. 897, Oct 1991.

    Google Scholar 

  29. B. Seshadri, I. Pomeranz, S. M. Reddy, S. Kundu, “On Path Selection For Delay Fault Testing Considering Operating Conditions”, Proceedings 8th IEEE European Test Workshop, pp. 141-146, May 2003.

    Google Scholar 

  30. N. Tendolkar, R. Molyneaux, C. Pyron, R. Raina, “At-Speed Testing Of Delay Faults For, Motorola s MPC7400, A PowerPCTM Microprocessor”, Proceedings 18th IEEE VLSI Test Symposium, pp. 3-8, April 2000.

    Google Scholar 

  31. B. Provost, T. Huang, C. H. Lim, K. Tian, M. Bashir, M. Atha, A. Muhtaroglu, C. Zhao, H. Muljono, “AC IO Loopback Design for High Speed uProcessor IO Test”, Proceedings International Test Conference, pp. 23-30, Oct 2004.

    Google Scholar 

  32. R. Aitken, “New Defect Behavior At 130nm And Beyond; Emerging Ideas Contribution, Extended Abstract”, Proceedings 9th European Test Symposium, pp. 279-284, May 2004.

    Google Scholar 

  33. P. Nigh, A. Gattiker, “Test Method Evaluation Experiments And Data”, Proceedings International Test Conference, pp. 454-463, Oct 2000.

    Google Scholar 

  34. B. Kruseman, A. Majhi, C. Hora, S. Eichenberger, J. Meirlevede, “Systematic Defects in Deep Sub-Micron Technologies”, Proceedings International Test Conference, pp. 290-299, Oct 2004.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer

About this chapter

Cite this chapter

Cron, A. (2006). Delay Testing. In: Gizopoulos, D. (eds) Gizopoulos / Advances in ElectronicTesting. Frontiers in Electronic Testing, vol 27. Springer, Boston, MA. https://doi.org/10.1007/0-387-29409-0_4

Download citation

  • DOI: https://doi.org/10.1007/0-387-29409-0_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-29408-7

  • Online ISBN: 978-0-387-29409-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics