This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
H.C. Poon, L.D. Yau, R.L. Johnston, D. Beecham, “DC Model for Short-Channel IGFET’s,” Intl. Electron Devices Meeting, pp. 156–159, Dec. 1973.
A. Asenov, G. Slavcheva, A.R. Brown, J.H. Davies, and S. Saini, “Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in Sub-100 nm MOSFETs due to Quantum Effects: A 3-D Density-Gradient Simulation Study,” IEEE Transactions on Electron Devices, vol. 48, no. 4, pp. 722–729, April 2001.
S. Narendra, D. Antoniadis, and V. De, “Impact of Using Adaptive Body Bias to Compensate Die-to-die Vt variation on Within-die Vt variation,” Intl. Symp. Low Power Electronics and Design, pp. 229–232, Aug. 1999.
M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, and K. Ishibashi, “A 1000-MIPS/W Microprocessor using Speed Adaptive Threshold-Voltage CMOS with Forward Bias,” Intl. Solid-State Circuits Conf., pp. 420–421, 2000.
V. De, “Forward Biased MOS Circuits,” United States Patent, Patent number: 6,166,584, Filed: June 1997, Issued: Dec. 2000.
C. Wann, J. Harrington, R. Mih, S. Biesemans, K. Han, R. Dennard, O. Prigge, C. Lin, R. Mahnkopf, and, B. Chen, “CMOS with Active Well Bias for Low-Power and RF/Analog Applications,” Symp. on VLSI Technology, pp. 158–159, 2000.
K. Bowman, S. Duvall, and J. Meindl, “Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution”, Intl. Solid-State Circuits Conf., pp. 278–279, 2001.
A. Keshavarzi, S. Narendra, B. Bloechel, S. Borkar, and V. De, “Forward Body Bias for Microprocessors in 130nm Technology Generation and Beyond,” Symp. on VLSI Circuits, 2002.
J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, “Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage,” Intl. Solid-State Circuits Conf., 2002.
S. Narendra et.al., “1.1V lGHz Communications Router with On-Chip Body B\ias in 150nm CMOS,” Intl. Solid-State Circuits Conf, 2002.
M. Haycock et.al., “3.2 GHz 6.4Gb/s per Wire Signaling in 0.18mm CMOS,” Intl. Solid-State Circuits Conf, pp. 62–63, 2001.
R. Nair et.al., “A 28.5 GB/s CMOS Non-Blocking Router for Terabits/s Connectivity between Multiple Processors and Peripheral I/O Nodes,” Intl. Solid-State Circuits Conf., pp. 224–225, 2001.
Y. Oowaki et.al., “A Sub-0.1μm Circuit Design with Substrate-over-Biasing,” Intl. Solid-State Circuits Conf., pp. 88–89, 1998.
H. Banba et.al., “A CMOS Band-gap Reference Circuit with Sub-lV operation,” Symp. on VLSI Circuits, pp. 228–229, 1998.
S. Vangal et.al., “5GHz 32-bit Integer Execution Core in 130nm Dual-Vt CMOS,” Intl. Solid-State Circuits Conf., 2002.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer Science+Business Media, Inc.
About this chapter
Cite this chapter
Narendra, S., Tschanz, J., Kao, J., Borkar, S., Chandrakasan, A., De, V. (2006). Process Variation and Adaptive Design. In: Leakage in Nanometer CMOS Technologies. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-28133-9_6
Download citation
DOI: https://doi.org/10.1007/0-387-28133-9_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-25737-2
Online ISBN: 978-0-387-28133-9
eBook Packages: EngineeringEngineering (R0)