Design Verification by At

Using Implicit Fault Model

In this chapter, we investigate methodology for simulation-based verification under a fault model. Since it is currently not feasible to describe a comprehensive explicit model of design errors, we propose an implicit fault model, which is based on the Arithmetic Transform (AT) spectral representation of faults. The verification of circuits under the assumption of small errors in spectral domain is then performed by the Universal Test Set (UTS) approach to test vector generation. The major result in this chapter shows that for errors whose AT has at most t nonzero coefficients, there exist the UTS test vector set of size O(n ^{log 1}₂ ). Consequently, verification confidence can be parameterized by the size of the error t, where at most OO(n ^{log 1}₂ ) verification vectors are simulated to prove the absence of a fault belonging to such an implicitly defined fault class. The experimental confirmation of the feasibility of the verification approach using this UTS method is presented, together with the relations between the Arithmetic and Walsh-Hadamard spectra. This will provide us with bounds the AT error spectrum, and show that a class of small error circuits has small error spectrum. The proposed approach has the advantage of compatibility with formal verification and testing methods.