SystemC as a Complete Design and Validation Environment

Abstract

Synthesis tools for SystemC descriptions are mature enough to cover the design flow from the system level to the gate level, whilst SystemC centered validation methodologies are still under development. This chapter presents a complete validation framework for SystemC designs based on a mix of functional testing and model checking. It is based on a fault model and a test generation strategy that are applicable through the whole design flow from system level to gate level. This is achieved by exploiting the SystemC 2.0 simulation efficiency and by performing an effective test patterns inheritance procedure. Fault simulation and automatic test pattern generation (ATPG) have been efficiently integrated into a unique C++ executable code linked to the SystemC model. In the case of mixed SystemC/HDL designs co-simulation is avoided by using a HDL to SystemC automatic translator, which produces a uniform executable SystemC model. Perturbed (faulty) SystemC descriptions are generated by injecting high-level faults into the code that are detected by using an ATPG. Undetected faults may be either faults hard to detect or design errors, thus they are further investigated by using model checking on the synthesized SystemC code. In this way the intrinsic characteristic of SystemC 2.0, in order to cover the whole design flow, is further extended by producing a SystemC-based validation environment that links a SystemC model with tools aiming at identifying design errors at all abstraction levels.