Chapter Summary
Links to layout is an important part of the integration between the layout tool and DC.This chapter focussed on all aspects of exchanging data to and from layout tools,in order for DC to perform better optimization and fine-tuning the design.
Issues related to transfer of clock tree information from the layout tool to DC were explained in detail.Cross checking the netlist generated by the layout tool against the original netlist remains a major bottleneck.Various alternatives were provided to the user in order to overcome this issue and choose the right solution.
Starting from how to generate a clean netlist from DC in order to minimize layout problems,this chapter covered placement and floorplanning,clock tree insertion,routing,extraction,and post-layout optimization techniques, including various methods to fix the hold-time violations.At each step, recommendations are provided to facilitate the user in choosing the right direction.
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© 2002 Kluwer Academic Publishers
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(2002). Links to Layout and Post Layout Optimization. In: Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®. Springer, Boston, MA. https://doi.org/10.1007/0-306-47507-3_9
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DOI: https://doi.org/10.1007/0-306-47507-3_9
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-7644-6
Online ISBN: 978-0-306-47507-8
eBook Packages: Springer Book Archive