Implementing processor arrays on FPGAs

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Abstract

Fine grain FPGAs offer a suitable medium for the implementation of bit level processor arrays. This paper describes a layout method, and a parametrized tool based on it, for designing two-dimensional array structures on FPGAs. The use of the tool is demonstrated by an example application in morphological image processing. The tool observes highlevel array structure, and thus it can find better layouts for arrays on the XC6216 FPGA, than the tool of the FPGA vendor (XACT 6000). Additionally, non-rectangular (distorted) layouts were found to perform better than rectangular ones.